--- old/usr/src/uts/armv6/loader/fakeloader.c	2015-02-12 20:32:16.820301208 -0500
+++ new/usr/src/uts/armv6/loader/fakeloader.c	2015-02-12 20:32:16.827689834 -0500
@@ -35,7 +35,7 @@
  *   		- boot_archive
  *   		- atags
  *   o Enable unaligned access
- *   o Enable the caches + virtual memory
+ *   o Enable virtual memory
  *
  * There are several important constraints that we have here:
  *
@@ -163,11 +163,18 @@
 	l1e = (arm_l1s_t *)pte;
 	*pte = 0;
 	l1e->al_type = ARMPT_L1_TYPE_SECT;
-	/* Assume it's not device memory */
-	l1e->al_bbit = 1;
-	l1e->al_cbit = 1;
-	l1e->al_tex = 1;
-	l1e->al_sbit = 1;
+
+	if (prot & PF_DEVICE) {
+		l1e->al_bbit = 1;
+		l1e->al_cbit = 0;
+		l1e->al_tex = 0;
+		l1e->al_sbit = 1;
+	} else {
+		l1e->al_bbit = 1;
+		l1e->al_cbit = 1;
+		l1e->al_tex = 1;
+		l1e->al_sbit = 1;
+	}
 
 	if (!(prot & PF_X))
 		l1e->al_xn = 1;
@@ -446,7 +453,7 @@
 
 			if (!(vstart & MMU_PAGEOFFSET1M) &&
 			    !(pstart & MMU_PAGEOFFSET1M) &&
-			    len == MMU_PAGESIZE1M) {
+			    len >= MMU_PAGESIZE1M) {
 				fakeload_map_1mb(pstart, vstart, prot);
 				vstart += MMU_PAGESIZE1M;
 				pstart += MMU_PAGESIZE1M;
@@ -703,10 +710,6 @@
 
 	FAKELOAD_DPRINTF("why helo thar\n");
 
-	/* Renable caches */
-	armv6_dcache_enable();
-	armv6_icache_enable();
-
 	/* we should never come back */
 	fakeload_exec(ident, ident2, chain, unix_start);
 	fakeload_panic("hit the end of the world\n");
--- old/usr/src/uts/armv6/loader/fakeloader_core.s	2015-02-12 20:32:17.062635803 -0500
+++ new/usr/src/uts/armv6/loader/fakeloader_core.s	2015-02-12 20:32:17.069961351 -0500
@@ -75,11 +75,18 @@
 	 * o Program the Page table root
 	 */
 	ENTRY(fakeload_pt_setup)
+	/* use TTBR0 only (should already be true) */
 	mov	r1, #0
 	mcr	p15, 0, r1, c2, c0, 2
+
+	/* set domain 0 to manager mode */
 	mov	r1, #3
 	mcr	p15, 0, r1, c3, c0, 0
-	orr	r0, r0, #0x1b
+
+	/* set TTBR0 to page table root */
+	orr	r0, r0, #0x18		/* Outer WB, no WA Cachable */
+	orr	r0, r0, #0x2		/* Sharable */
+	orr	r0, r0, #0x1		/* Inner Cachable */
 	mcr	p15, 0, r0, c2, c0, 0
 	bx	lr
 	SET_SIZE(fakeload_pt_setup)
@@ -101,10 +108,8 @@
 	 */
 	ENTRY(fakeload_mmu_enable)
 	mrc	p15, 0, r0, c1, c0, 0
-	orr	r0, #0x800000
-	mcr	p15, 0, r0, c1, c0, 0
-	mrc	p15, 0, r0, c1, c0, 0
-	orr	r0, #0x1
+	orr	r0, #0x800000		/* enable ARMv6 pages */
+	orr	r0, #0x1		/* enable MMU */
 	mcr	p15, 0, r0, c1, c0, 0
 	bx	lr
 	SET_SIZE(fakeload_mmu_enable)
--- old/usr/src/uts/armv6/ml/cache.s	2015-02-12 20:32:17.271954429 -0500
+++ new/usr/src/uts/armv6/ml/cache.s	2015-02-12 20:32:17.279309819 -0500
@@ -189,17 +189,20 @@
 	SET_SIZE(armv6_dcache_disable)
 
 	ENTRY(armv6_icache_inval)
+	mov	r0, #0
 	mcr	p15, 0, r0, c7, c5, 0		@ Invalidate i-cache
 	bx	lr
 	SET_SIZE(armv6_icache_inval)
 
 	ENTRY(armv6_dcache_inval)
+	mov	r0, #0
 	mcr	p15, 0, r0, c7, c6, 0		@ Invalidate d-cache
 	ARM_DSB_INSTR(r2)
 	bx	lr
 	SET_SIZE(armv6_dcache_inval)
 
 	ENTRY(armv6_dcache_flush)
+	mov	r0, #0
 	mcr	p15, 0, r0, c7, c10, 4		@ Flush d-cache
 	ARM_DSB_INSTR(r2)
 	bx	lr
@@ -216,6 +219,7 @@
 	SET_SIZE(armv6_text_flush_range)
 
 	ENTRY(armv6_text_flush)
+	mov	r0, #0
 	mcr	p15, 0, r0, c7, c5, 0		@ Invalidate i-cache
 	mcr	p15, 0, r0, c7, c10, 4		@ Flush d-cache
 	ARM_DSB_INSTR(r2)
--- old/usr/src/uts/armv6/ml/glocore.s	2015-02-12 20:32:17.482815851 -0500
+++ new/usr/src/uts/armv6/ml/glocore.s	2015-02-12 20:32:17.490302794 -0500
@@ -42,7 +42,7 @@
  *   - a UART has been enabled & any memory mapped registers have been 1:1
  *     mapped
  *   - ATAGs have been updated to tell us what the mappings are
- * - I/D L1 caches have been enabled
+ * - I/D L1 caches have may be disabled
  */
 
 	/*
@@ -89,6 +89,20 @@
 	orr	r3, r3, #(1 << 13)
 	mcr	p15, 0, r3, c1, c0, 0
 
+	/*
+	 * Go ahead now and enable the L1 I/D caches.  (Involves
+	 * invalidating the caches and the TLB.)
+	 */
+	mov	r4, #0
+	mov	r5, #0
+	mcr	p15, 0, r4, c7, c7, 0	/* invalidate caches */
+	mcr	p15, 0, r4, c8, c7, 0	/* invalidate tlb */
+	mcr	p15, 0, r5, c7, c10, 4	/* DSB */
+	mrc	p15, 0, r4, c1, c0, 0
+	orr	r4, #0x04	/* D-cache */
+	orr	r4, #0x1000	/* I-cache */
+	mcr	p15, 0, r4, c1, c0, 0
+
 	/* invoke machine specific setup */
 	bl	_mach_start
 
@@ -111,7 +125,6 @@
 	 * then main. We're never going back so we shouldn't feel compelled to
 	 * preserve any registers.
 	 *
-	 *  o Enable our I/D-caches
 	 *  o Save the boot syscalls and bootops for later
 	 *  o Set up our stack to be the real stack of t0stack.
 	 *  o Save t0 as curthread
@@ -162,14 +175,6 @@
 	mcr	p15, 0, r0, c13, c0, 4
 
 	/*
-	 * Go ahead now and enable the L1 I/D caches.  
-	 */
-	mrc	p15, 0, r0, c1, c0, 0
-	orr	r0, #0x04	/* D-cache */
-	orr	r0, #0x1000	/* I-cache */
-	mcr	p15, 0, r0, c1, c0, 0
-
-	/*
 	 * mlsetup() takes the struct regs as an argument. main doesn't take
 	 * any and should never return. Currently, we have an 8-byte aligned
 	 * stack.  We want to push a zero frame pointer to terminate any
