Print this page
5253 kmem_alloc/kmem_zalloc won't fail with KM_SLEEP
5254 getrbuf won't fail with KM_SLEEP
| Split |
Close |
| Expand all |
| Collapse all |
--- old/usr/src/uts/common/io/mwl/mwl.c
+++ new/usr/src/uts/common/io/mwl/mwl.c
1 1 /*
2 2 * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
3 3 * Use is subject to license terms.
4 4 */
5 5
6 6 /*
7 7 * Copyright (c) 2007-2009 Sam Leffler, Errno Consulting
8 8 * Copyright (c) 2007-2008 Marvell Semiconductor, Inc.
9 9 * All rights reserved.
10 10 *
11 11 * Redistribution and use in source and binary forms, with or without
12 12 * modification, are permitted provided that the following conditions
13 13 * are met:
14 14 * 1. Redistributions of source code must retain the above copyright
15 15 * notice, this list of conditions and the following disclaimer,
16 16 * without modification.
17 17 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
18 18 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
19 19 * redistribution must be conditioned upon including a substantially
20 20 * similar Disclaimer requirement for further binary redistribution.
21 21 *
22 22 * NO WARRANTY
23 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
24 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
25 25 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
26 26 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
27 27 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
28 28 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
31 31 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 33 * THE POSSIBILITY OF SUCH DAMAGES.
34 34 */
35 35
36 36 /*
37 37 * Driver for the Marvell 88W8363 Wireless LAN controller.
38 38 */
39 39 #include <sys/stat.h>
40 40 #include <sys/dlpi.h>
41 41 #include <inet/common.h>
42 42 #include <inet/mi.h>
43 43 #include <sys/stream.h>
44 44 #include <sys/errno.h>
45 45 #include <sys/stropts.h>
46 46 #include <sys/stat.h>
47 47 #include <sys/sunddi.h>
48 48 #include <sys/strsubr.h>
49 49 #include <sys/strsun.h>
50 50 #include <sys/pci.h>
51 51 #include <sys/mac_provider.h>
52 52 #include <sys/mac_wifi.h>
53 53 #include <sys/net80211.h>
54 54 #include <inet/wifi_ioctl.h>
55 55
56 56 #include "mwl_var.h"
57 57
58 58 static int mwl_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd);
59 59 static int mwl_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd);
60 60 static int mwl_quiesce(dev_info_t *devinfo);
61 61
62 62 DDI_DEFINE_STREAM_OPS(mwl_dev_ops, nulldev, nulldev, mwl_attach, mwl_detach,
63 63 nodev, NULL, D_MP, NULL, mwl_quiesce);
64 64
65 65 static struct modldrv mwl_modldrv = {
66 66 &mod_driverops, /* Type of module. This one is a driver */
67 67 "Marvell 88W8363 WiFi driver v1.1", /* short description */
68 68 &mwl_dev_ops /* driver specific ops */
69 69 };
70 70
71 71 static struct modlinkage modlinkage = {
72 72 MODREV_1, (void *)&mwl_modldrv, NULL
73 73 };
74 74
75 75 static void *mwl_soft_state_p = NULL;
76 76
77 77 static int mwl_m_stat(void *, uint_t, uint64_t *);
78 78 static int mwl_m_start(void *);
79 79 static void mwl_m_stop(void *);
80 80 static int mwl_m_promisc(void *, boolean_t);
81 81 static int mwl_m_multicst(void *, boolean_t, const uint8_t *);
82 82 static int mwl_m_unicst(void *, const uint8_t *);
83 83 static mblk_t *mwl_m_tx(void *, mblk_t *);
84 84 static void mwl_m_ioctl(void *, queue_t *, mblk_t *);
85 85 static int mwl_m_setprop(void *arg, const char *pr_name,
86 86 mac_prop_id_t wldp_pr_num,
87 87 uint_t wldp_length, const void *wldp_buf);
88 88 static int mwl_m_getprop(void *arg, const char *pr_name,
89 89 mac_prop_id_t wldp_pr_num, uint_t wldp_length,
90 90 void *wldp_buf);
91 91 static void mwl_m_propinfo(void *, const char *, mac_prop_id_t,
92 92 mac_prop_info_handle_t);
93 93
94 94 static mac_callbacks_t mwl_m_callbacks = {
95 95 MC_IOCTL | MC_SETPROP | MC_GETPROP | MC_PROPINFO,
96 96 mwl_m_stat,
97 97 mwl_m_start,
98 98 mwl_m_stop,
99 99 mwl_m_promisc,
100 100 mwl_m_multicst,
101 101 mwl_m_unicst,
102 102 mwl_m_tx,
103 103 NULL,
104 104 mwl_m_ioctl,
105 105 NULL,
106 106 NULL,
107 107 NULL,
108 108 mwl_m_setprop,
109 109 mwl_m_getprop,
110 110 mwl_m_propinfo
111 111 };
112 112
113 113 #define MWL_DBG_ATTACH (1 << 0)
114 114 #define MWL_DBG_DMA (1 << 1)
115 115 #define MWL_DBG_FW (1 << 2)
116 116 #define MWL_DBG_HW (1 << 3)
117 117 #define MWL_DBG_INTR (1 << 4)
118 118 #define MWL_DBG_RX (1 << 5)
119 119 #define MWL_DBG_TX (1 << 6)
120 120 #define MWL_DBG_CMD (1 << 7)
121 121 #define MWL_DBG_CRYPTO (1 << 8)
122 122 #define MWL_DBG_SR (1 << 9)
123 123 #define MWL_DBG_MSG (1 << 10)
124 124
125 125 uint32_t mwl_dbg_flags = 0x0;
126 126
127 127 #ifdef DEBUG
128 128 #define MWL_DBG \
129 129 mwl_debug
130 130 #else
131 131 #define MWL_DBG
132 132 #endif
133 133
134 134 /*
135 135 * PIO access attributes for registers
136 136 */
137 137 static ddi_device_acc_attr_t mwl_reg_accattr = {
138 138 DDI_DEVICE_ATTR_V0,
139 139 DDI_STRUCTURE_LE_ACC,
140 140 DDI_STRICTORDER_ACC,
141 141 DDI_DEFAULT_ACC
142 142 };
143 143
144 144 static ddi_device_acc_attr_t mwl_cmdbuf_accattr = {
145 145 DDI_DEVICE_ATTR_V0,
146 146 DDI_NEVERSWAP_ACC,
147 147 DDI_STRICTORDER_ACC,
148 148 DDI_DEFAULT_ACC
149 149 };
150 150
151 151 /*
152 152 * DMA access attributes for descriptors and bufs: NOT to be byte swapped.
153 153 */
154 154 static ddi_device_acc_attr_t mwl_desc_accattr = {
155 155 DDI_DEVICE_ATTR_V0,
156 156 DDI_NEVERSWAP_ACC,
157 157 DDI_STRICTORDER_ACC,
158 158 DDI_DEFAULT_ACC
159 159 };
160 160
161 161 static ddi_device_acc_attr_t mwl_buf_accattr = {
162 162 DDI_DEVICE_ATTR_V0,
163 163 DDI_NEVERSWAP_ACC,
164 164 DDI_STRICTORDER_ACC,
165 165 DDI_DEFAULT_ACC
166 166 };
167 167
168 168 /*
169 169 * Describes the chip's DMA engine
170 170 */
171 171 static ddi_dma_attr_t mwl_dma_attr = {
172 172 DMA_ATTR_V0, /* dma_attr version */
173 173 0x0000000000000000ull, /* dma_attr_addr_lo */
174 174 0xFFFFFFFF, /* dma_attr_addr_hi */
175 175 0x00000000FFFFFFFFull, /* dma_attr_count_max */
176 176 0x0000000000000001ull, /* dma_attr_align */
177 177 0x00000FFF, /* dma_attr_burstsizes */
178 178 0x00000001, /* dma_attr_minxfer */
179 179 0x000000000000FFFFull, /* dma_attr_maxxfer */
180 180 0xFFFFFFFFFFFFFFFFull, /* dma_attr_seg */
181 181 1, /* dma_attr_sgllen */
182 182 0x00000001, /* dma_attr_granular */
183 183 0 /* dma_attr_flags */
184 184 };
185 185
186 186 /*
187 187 * Supported rates for 802.11a/b/g modes (in 500Kbps unit).
188 188 */
189 189 static const struct ieee80211_rateset mwl_rateset_11b =
190 190 { 4, { 2, 4, 11, 22 } };
191 191
192 192 static const struct ieee80211_rateset mwl_rateset_11g =
193 193 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } };
194 194
195 195 static int mwl_alloc_dma_mem(dev_info_t *, ddi_dma_attr_t *, size_t,
196 196 ddi_device_acc_attr_t *, uint_t, uint_t,
197 197 struct dma_area *);
198 198 static void mwl_free_dma_mem(struct dma_area *);
199 199 static int mwl_alloc_cmdbuf(struct mwl_softc *);
200 200 static void mwl_free_cmdbuf(struct mwl_softc *);
201 201 static int mwl_alloc_rx_ring(struct mwl_softc *, int);
202 202 static void mwl_free_rx_ring(struct mwl_softc *);
203 203 static int mwl_alloc_tx_ring(struct mwl_softc *, struct mwl_tx_ring *,
204 204 int);
205 205 static void mwl_free_tx_ring(struct mwl_softc *, struct mwl_tx_ring *);
206 206 static int mwl_setupdma(struct mwl_softc *);
207 207 static void mwl_txq_init(struct mwl_softc *, struct mwl_tx_ring *, int);
208 208 static int mwl_tx_setup(struct mwl_softc *, int, int);
209 209 static int mwl_setup_txq(struct mwl_softc *);
210 210 static int mwl_fwload(struct mwl_softc *, void *);
211 211 static int mwl_loadsym(ddi_modhandle_t, char *, char **, size_t *);
212 212 static void mwlFwReset(struct mwl_softc *);
213 213 static void mwlPokeSdramController(struct mwl_softc *, int);
214 214 static void mwlTriggerPciCmd(struct mwl_softc *);
215 215 static int mwlWaitFor(struct mwl_softc *, uint32_t);
216 216 static int mwlSendBlock(struct mwl_softc *, int, const void *, size_t);
217 217 static int mwlSendBlock2(struct mwl_softc *, const void *, size_t);
218 218 static void mwlSendCmd(struct mwl_softc *);
219 219 static int mwlExecuteCmd(struct mwl_softc *, unsigned short);
220 220 static int mwlWaitForCmdComplete(struct mwl_softc *, uint16_t);
221 221 static void dumpresult(struct mwl_softc *, int);
222 222 static int mwlResetHalState(struct mwl_softc *);
223 223 static int mwlGetPwrCalTable(struct mwl_softc *);
224 224 static int mwlGetCalTable(struct mwl_softc *, uint8_t, uint8_t);
225 225 static int mwlGetPwrCalTable(struct mwl_softc *);
226 226 static void dumpcaldata(const char *, const uint8_t *, int);
227 227 static void get2Ghz(MWL_HAL_CHANNELINFO *, const uint8_t *, int);
228 228 static void get5Ghz(MWL_HAL_CHANNELINFO *, const uint8_t *, int);
229 229 static void setmaxtxpow(struct mwl_hal_channel *, int, int);
230 230 static uint16_t ieee2mhz(int);
231 231 static const char *
232 232 mwlcmdname(int);
233 233 static int mwl_gethwspecs(struct mwl_softc *);
234 234 static int mwl_getchannels(struct mwl_softc *);
235 235 static void getchannels(struct mwl_softc *, int, int *,
236 236 struct mwl_channel *);
237 237 static void addchannels(struct mwl_channel *, int, int *,
238 238 const MWL_HAL_CHANNELINFO *, int);
239 239 static void addht40channels(struct mwl_channel *, int, int *,
240 240 const MWL_HAL_CHANNELINFO *, int);
241 241 static const struct mwl_channel *
242 242 findchannel(const struct mwl_channel *, int,
243 243 int, int);
244 244 static void addchan(struct mwl_channel *, int, int, int, int);
245 245
246 246 static int mwl_chan_set(struct mwl_softc *, struct mwl_channel *);
247 247 static void mwl_mapchan(MWL_HAL_CHANNEL *, const struct mwl_channel *);
248 248 static int mwl_setcurchanrates(struct mwl_softc *);
249 249 const struct ieee80211_rateset *
250 250 mwl_get_suprates(struct ieee80211com *,
251 251 const struct mwl_channel *);
252 252 static uint32_t cvtChannelFlags(const MWL_HAL_CHANNEL *);
253 253 static const struct mwl_hal_channel *
254 254 findhalchannel(const struct mwl_softc *,
255 255 const MWL_HAL_CHANNEL *);
256 256 enum ieee80211_phymode
257 257 mwl_chan2mode(const struct mwl_channel *);
258 258 static int mwl_map2regioncode(const struct mwl_regdomain *);
259 259 static int mwl_startrecv(struct mwl_softc *);
260 260 static int mwl_mode_init(struct mwl_softc *);
261 261 static void mwl_hal_intrset(struct mwl_softc *, uint32_t);
262 262 static void mwl_hal_getisr(struct mwl_softc *, uint32_t *);
263 263 static int mwl_hal_sethwdma(struct mwl_softc *,
264 264 const struct mwl_hal_txrxdma *);
265 265 static int mwl_hal_getchannelinfo(struct mwl_softc *, int, int,
266 266 const MWL_HAL_CHANNELINFO **);
267 267 static int mwl_hal_setmac_locked(struct mwl_softc *, const uint8_t *);
268 268 static int mwl_hal_keyreset(struct mwl_softc *, const MWL_HAL_KEYVAL *,
269 269 const uint8_t mac[IEEE80211_ADDR_LEN]);
270 270 static int mwl_hal_keyset(struct mwl_softc *, const MWL_HAL_KEYVAL *,
271 271 const uint8_t mac[IEEE80211_ADDR_LEN]);
272 272 static int mwl_hal_newstation(struct mwl_softc *, const uint8_t *,
273 273 uint16_t, uint16_t, const MWL_HAL_PEERINFO *, int, int);
274 274 static int mwl_hal_setantenna(struct mwl_softc *, MWL_HAL_ANTENNA, int);
275 275 static int mwl_hal_setradio(struct mwl_softc *, int, MWL_HAL_PREAMBLE);
276 276 static int mwl_hal_setwmm(struct mwl_softc *, int);
277 277 static int mwl_hal_setchannel(struct mwl_softc *, const MWL_HAL_CHANNEL *);
278 278 static int mwl_hal_settxpower(struct mwl_softc *, const MWL_HAL_CHANNEL *,
279 279 uint8_t);
280 280 static int mwl_hal_settxrate(struct mwl_softc *, MWL_HAL_TXRATE_HANDLING,
281 281 const MWL_HAL_TXRATE *);
282 282 static int mwl_hal_settxrate_auto(struct mwl_softc *,
283 283 const MWL_HAL_TXRATE *);
284 284 static int mwl_hal_setrateadaptmode(struct mwl_softc *, uint16_t);
285 285 static int mwl_hal_setoptimizationlevel(struct mwl_softc *, int);
286 286 static int mwl_hal_setregioncode(struct mwl_softc *, int);
287 287 static int mwl_hal_setassocid(struct mwl_softc *, const uint8_t *,
288 288 uint16_t);
289 289 static int mwl_setrates(struct ieee80211com *);
290 290 static int mwl_hal_setrtsthreshold(struct mwl_softc *, int);
291 291 static int mwl_hal_setcsmode(struct mwl_softc *, MWL_HAL_CSMODE);
292 292 static int mwl_hal_setpromisc(struct mwl_softc *, int);
293 293 static int mwl_hal_start(struct mwl_softc *);
294 294 static int mwl_hal_setinframode(struct mwl_softc *);
295 295 static int mwl_hal_stop(struct mwl_softc *);
296 296 static struct ieee80211_node *
297 297 mwl_node_alloc(struct ieee80211com *);
298 298 static void mwl_node_free(struct ieee80211_node *);
299 299 static int mwl_key_alloc(struct ieee80211com *,
300 300 const struct ieee80211_key *,
301 301 ieee80211_keyix *, ieee80211_keyix *);
302 302 static int mwl_key_delete(struct ieee80211com *,
303 303 const struct ieee80211_key *);
304 304 static int mwl_key_set(struct ieee80211com *, const struct ieee80211_key *,
305 305 const uint8_t mac[IEEE80211_ADDR_LEN]);
306 306 static void mwl_setanywepkey(struct ieee80211com *, const uint8_t *);
307 307 static void mwl_setglobalkeys(struct ieee80211com *c);
308 308 static int addgroupflags(MWL_HAL_KEYVAL *, const struct ieee80211_key *);
309 309 static void mwl_hal_txstart(struct mwl_softc *, int);
310 310 static int mwl_send(ieee80211com_t *, mblk_t *, uint8_t);
311 311 static void mwl_next_scan(void *);
312 312 static MWL_HAL_PEERINFO *
313 313 mkpeerinfo(MWL_HAL_PEERINFO *, const struct ieee80211_node *);
314 314 static uint32_t get_rate_bitmap(const struct ieee80211_rateset *);
315 315 static int mwl_newstate(struct ieee80211com *, enum ieee80211_state, int);
316 316 static int cvtrssi(uint8_t);
317 317 static uint_t mwl_intr(caddr_t, caddr_t);
318 318 static uint_t mwl_softintr(caddr_t, caddr_t);
319 319 static void mwl_tx_intr(struct mwl_softc *);
320 320 static void mwl_rx_intr(struct mwl_softc *);
321 321 static int mwl_init(struct mwl_softc *);
322 322 static void mwl_stop(struct mwl_softc *);
323 323 static int mwl_resume(struct mwl_softc *);
324 324
325 325
326 326 #ifdef DEBUG
327 327 static void
328 328 mwl_debug(uint32_t dbg_flags, const int8_t *fmt, ...)
329 329 {
330 330 va_list args;
331 331
332 332 if (dbg_flags & mwl_dbg_flags) {
333 333 va_start(args, fmt);
334 334 vcmn_err(CE_CONT, fmt, args);
335 335 va_end(args);
336 336 }
337 337 }
338 338 #endif
339 339
340 340 /*
341 341 * Allocate an DMA memory and a DMA handle for accessing it
342 342 */
343 343 static int
344 344 mwl_alloc_dma_mem(dev_info_t *devinfo, ddi_dma_attr_t *dma_attr,
345 345 size_t memsize, ddi_device_acc_attr_t *attr_p, uint_t alloc_flags,
346 346 uint_t bind_flags, struct dma_area *dma_p)
347 347 {
348 348 int err;
349 349
350 350 /*
351 351 * Allocate handle
352 352 */
353 353 err = ddi_dma_alloc_handle(devinfo, dma_attr,
354 354 DDI_DMA_SLEEP, NULL, &dma_p->dma_hdl);
355 355 if (err != DDI_SUCCESS) {
356 356 MWL_DBG(MWL_DBG_DMA, "mwl: mwl_alloc_dma_mem(): "
357 357 "failed to alloc handle\n");
358 358 goto fail1;
359 359 }
360 360
361 361 /*
362 362 * Allocate memory
363 363 */
364 364 err = ddi_dma_mem_alloc(dma_p->dma_hdl, memsize, attr_p,
365 365 alloc_flags, DDI_DMA_SLEEP, NULL, &dma_p->mem_va,
366 366 &dma_p->alength, &dma_p->acc_hdl);
367 367 if (err != DDI_SUCCESS) {
368 368 MWL_DBG(MWL_DBG_DMA, "mwl: mwl_alloc_dma_mem(): "
369 369 "failed to alloc mem\n");
370 370 goto fail2;
371 371 }
372 372
373 373 /*
374 374 * Bind the two together
375 375 */
376 376 err = ddi_dma_addr_bind_handle(dma_p->dma_hdl, NULL,
377 377 dma_p->mem_va, dma_p->alength, bind_flags,
378 378 DDI_DMA_SLEEP, NULL, &dma_p->cookie, &dma_p->ncookies);
379 379 if (err != DDI_DMA_MAPPED) {
380 380 MWL_DBG(MWL_DBG_DMA, "mwl: mwl_alloc_dma_mem(): "
381 381 "failed to bind handle\n");
382 382 goto fail3;
383 383 }
384 384
385 385 if (dma_p->ncookies != 1) {
386 386 MWL_DBG(MWL_DBG_DMA, "mwl: mwl_alloc_dma_mem(): "
387 387 "failed to alloc cookies\n");
388 388 goto fail4;
389 389 }
390 390
391 391 dma_p->nslots = ~0U;
392 392 dma_p->size = ~0U;
393 393 dma_p->token = ~0U;
394 394 dma_p->offset = 0;
395 395
396 396 return (DDI_SUCCESS);
397 397
398 398 fail4:
399 399 (void) ddi_dma_unbind_handle(dma_p->dma_hdl);
400 400 fail3:
401 401 ddi_dma_mem_free(&dma_p->acc_hdl);
402 402 fail2:
403 403 ddi_dma_free_handle(&dma_p->dma_hdl);
404 404 fail1:
405 405 return (err);
406 406 }
407 407
408 408 static void
409 409 mwl_free_dma_mem(struct dma_area *dma_p)
410 410 {
411 411 if (dma_p->dma_hdl != NULL) {
412 412 (void) ddi_dma_unbind_handle(dma_p->dma_hdl);
413 413 if (dma_p->acc_hdl != NULL) {
414 414 ddi_dma_mem_free(&dma_p->acc_hdl);
415 415 dma_p->acc_hdl = NULL;
416 416 }
417 417 ddi_dma_free_handle(&dma_p->dma_hdl);
418 418 dma_p->ncookies = 0;
419 419 dma_p->dma_hdl = NULL;
420 420 }
421 421 }
422 422
423 423 static int
424 424 mwl_alloc_cmdbuf(struct mwl_softc *sc)
425 425 {
426 426 int err;
427 427 size_t size;
428 428
429 429 size = MWL_CMDBUF_SIZE;
430 430
431 431 err = mwl_alloc_dma_mem(sc->sc_dev, &mwl_dma_attr, size,
432 432 &mwl_cmdbuf_accattr, DDI_DMA_CONSISTENT,
433 433 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
434 434 &sc->sc_cmd_dma);
435 435 if (err != DDI_SUCCESS) {
436 436 MWL_DBG(MWL_DBG_DMA, "mwl: mwl_alloc_cmdbuf(): "
437 437 "failed to alloc dma mem\n");
438 438 return (DDI_FAILURE);
439 439 }
440 440
441 441 sc->sc_cmd_mem = (uint16_t *)sc->sc_cmd_dma.mem_va;
442 442 sc->sc_cmd_dmaaddr = sc->sc_cmd_dma.cookie.dmac_address;
443 443
444 444 return (DDI_SUCCESS);
445 445 }
446 446
447 447 static void
448 448 mwl_free_cmdbuf(struct mwl_softc *sc)
449 449 {
450 450 if (sc->sc_cmd_mem != NULL)
451 451 mwl_free_dma_mem(&sc->sc_cmd_dma);
452 452 }
453 453
454 454 static int
455 455 mwl_alloc_rx_ring(struct mwl_softc *sc, int count)
456 456 {
457 457 struct mwl_rx_ring *ring;
458 458 struct mwl_rxdesc *ds;
459 459 struct mwl_rxbuf *bf;
460 460 int i, err, datadlen;
461 461
462 462 ring = &sc->sc_rxring;
463 463 ring->count = count;
464 464 ring->cur = ring->next = 0;
465 465 err = mwl_alloc_dma_mem(sc->sc_dev, &mwl_dma_attr,
466 466 count * sizeof (struct mwl_rxdesc),
467 467 &mwl_desc_accattr,
468 468 DDI_DMA_CONSISTENT, DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
469 469 &ring->rxdesc_dma);
470 470 if (err) {
471 471 MWL_DBG(MWL_DBG_DMA, "mwl: mwl_alloc_rxring(): "
472 472 "alloc tx ring failed, size %d\n",
473 473 (uint32_t)(count * sizeof (struct mwl_rxdesc)));
474 474 return (DDI_FAILURE);
475 475 }
476 476
477 477 MWL_DBG(MWL_DBG_DMA, "mwl: mwl_alloc_rx_ring(): "
478 478 "dma len = %d\n", (uint32_t)(ring->rxdesc_dma.alength));
479 479 ring->desc = (struct mwl_rxdesc *)ring->rxdesc_dma.mem_va;
480 480 ring->physaddr = ring->rxdesc_dma.cookie.dmac_address;
481 481 bzero(ring->desc, count * sizeof (struct mwl_rxdesc));
482 482
483 483 datadlen = count * sizeof (struct mwl_rxbuf);
484 484 ring->buf = (struct mwl_rxbuf *)kmem_zalloc(datadlen, KM_SLEEP);
485 485 if (ring->buf == NULL) {
486 486 MWL_DBG(MWL_DBG_DMA, "mwl: mwl_alloc_rxring(): "
487 487 "could not alloc rx ring data buffer\n");
488 488 return (DDI_FAILURE);
489 489 }
490 490 bzero(ring->buf, count * sizeof (struct mwl_rxbuf));
491 491
492 492 /*
493 493 * Pre-allocate Rx buffers and populate Rx ring.
494 494 */
495 495 for (i = 0; i < count; i++) {
496 496 ds = &ring->desc[i];
497 497 bf = &ring->buf[i];
498 498 /* alloc DMA memory */
499 499 (void) mwl_alloc_dma_mem(sc->sc_dev, &mwl_dma_attr,
500 500 sc->sc_dmabuf_size,
501 501 &mwl_buf_accattr,
502 502 DDI_DMA_STREAMING,
503 503 DDI_DMA_READ | DDI_DMA_STREAMING,
504 504 &bf->rxbuf_dma);
505 505 bf->bf_mem = (uint8_t *)(bf->rxbuf_dma.mem_va);
506 506 bf->bf_baddr = bf->rxbuf_dma.cookie.dmac_address;
507 507 bf->bf_desc = ds;
508 508 bf->bf_daddr = ring->physaddr + _PTRDIFF(ds, ring->desc);
509 509 }
510 510
511 511 (void) ddi_dma_sync(ring->rxdesc_dma.dma_hdl,
512 512 0,
513 513 ring->rxdesc_dma.alength,
514 514 DDI_DMA_SYNC_FORDEV);
515 515
516 516 return (0);
517 517 }
518 518
519 519 static void
520 520 mwl_free_rx_ring(struct mwl_softc *sc)
521 521 {
522 522 struct mwl_rx_ring *ring;
523 523 struct mwl_rxbuf *bf;
524 524 int i;
525 525
526 526 ring = &sc->sc_rxring;
527 527
528 528 if (ring->desc != NULL) {
529 529 mwl_free_dma_mem(&ring->rxdesc_dma);
530 530 }
531 531
532 532 if (ring->buf != NULL) {
533 533 for (i = 0; i < ring->count; i++) {
534 534 bf = &ring->buf[i];
535 535 mwl_free_dma_mem(&bf->rxbuf_dma);
536 536 }
537 537 kmem_free(ring->buf,
538 538 (ring->count * sizeof (struct mwl_rxbuf)));
539 539 }
540 540 }
541 541
542 542 static int
543 543 mwl_alloc_tx_ring(struct mwl_softc *sc, struct mwl_tx_ring *ring,
544 544 int count)
545 545 {
546 546 struct mwl_txdesc *ds;
547 547 struct mwl_txbuf *bf;
548 548 int i, err, datadlen;
549 549
550 550 ring->count = count;
551 551 ring->queued = 0;
552 552 ring->cur = ring->next = ring->stat = 0;
553 553 err = mwl_alloc_dma_mem(sc->sc_dev, &mwl_dma_attr,
554 554 count * sizeof (struct mwl_txdesc), &mwl_desc_accattr,
555 555 DDI_DMA_CONSISTENT, DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
556 556 &ring->txdesc_dma);
557 557 if (err) {
558 558 MWL_DBG(MWL_DBG_DMA, "mwl: mwl_alloc_tx_ring(): "
559 559 "alloc tx ring failed, size %d\n",
560 560 (uint32_t)(count * sizeof (struct mwl_txdesc)));
561 561 return (DDI_FAILURE);
|
↓ open down ↓ |
561 lines elided |
↑ open up ↑ |
562 562 }
563 563
564 564 MWL_DBG(MWL_DBG_DMA, "mwl: mwl_alloc_tx_ring(): "
565 565 "dma len = %d\n", (uint32_t)(ring->txdesc_dma.alength));
566 566 ring->desc = (struct mwl_txdesc *)ring->txdesc_dma.mem_va;
567 567 ring->physaddr = ring->txdesc_dma.cookie.dmac_address;
568 568 bzero(ring->desc, count * sizeof (struct mwl_txdesc));
569 569
570 570 datadlen = count * sizeof (struct mwl_txbuf);
571 571 ring->buf = kmem_zalloc(datadlen, KM_SLEEP);
572 - if (ring->buf == NULL) {
573 - MWL_DBG(MWL_DBG_DMA, "mwl: mwl_alloc_tx_ring(): "
574 - "could not alloc tx ring data buffer\n");
575 - return (DDI_FAILURE);
576 - }
577 572 bzero(ring->buf, count * sizeof (struct mwl_txbuf));
578 573
579 574 for (i = 0; i < count; i++) {
580 575 ds = &ring->desc[i];
581 576 bf = &ring->buf[i];
582 577 /* alloc DMA memory */
583 578 (void) mwl_alloc_dma_mem(sc->sc_dev, &mwl_dma_attr,
584 579 sc->sc_dmabuf_size,
585 580 &mwl_buf_accattr,
586 581 DDI_DMA_STREAMING,
587 582 DDI_DMA_WRITE | DDI_DMA_STREAMING,
588 583 &bf->txbuf_dma);
589 584 bf->bf_baddr = bf->txbuf_dma.cookie.dmac_address;
590 585 bf->bf_mem = (uint8_t *)(bf->txbuf_dma.mem_va);
591 586 bf->bf_daddr = ring->physaddr + _PTRDIFF(ds, ring->desc);
592 587 bf->bf_desc = ds;
593 588 }
594 589
595 590 (void) ddi_dma_sync(ring->txdesc_dma.dma_hdl,
596 591 0,
597 592 ring->txdesc_dma.alength,
598 593 DDI_DMA_SYNC_FORDEV);
599 594
600 595 return (0);
601 596 }
602 597
603 598 /* ARGSUSED */
604 599 static void
605 600 mwl_free_tx_ring(struct mwl_softc *sc, struct mwl_tx_ring *ring)
606 601 {
607 602 struct mwl_txbuf *bf;
608 603 int i;
609 604
610 605 if (ring->desc != NULL) {
611 606 mwl_free_dma_mem(&ring->txdesc_dma);
612 607 }
613 608
614 609 if (ring->buf != NULL) {
615 610 for (i = 0; i < ring->count; i++) {
616 611 bf = &ring->buf[i];
617 612 mwl_free_dma_mem(&bf->txbuf_dma);
618 613 }
619 614 kmem_free(ring->buf,
620 615 (ring->count * sizeof (struct mwl_txbuf)));
621 616 }
622 617 }
623 618
624 619 /*
625 620 * Inform the f/w about location of the tx/rx dma data structures
626 621 * and related state. This cmd must be done immediately after a
627 622 * mwl_hal_gethwspecs call or the f/w will lockup.
628 623 */
629 624 static int
630 625 mwl_hal_sethwdma(struct mwl_softc *sc, const struct mwl_hal_txrxdma *dma)
631 626 {
632 627 HostCmd_DS_SET_HW_SPEC *pCmd;
633 628 int retval;
634 629
635 630 _CMD_SETUP(pCmd, HostCmd_DS_SET_HW_SPEC, HostCmd_CMD_SET_HW_SPEC);
636 631 pCmd->WcbBase[0] = LE_32(dma->wcbBase[0]);
637 632 pCmd->WcbBase[1] = LE_32(dma->wcbBase[1]);
638 633 pCmd->WcbBase[2] = LE_32(dma->wcbBase[2]);
639 634 pCmd->WcbBase[3] = LE_32(dma->wcbBase[3]);
640 635 pCmd->TxWcbNumPerQueue = LE_32(dma->maxNumTxWcb);
641 636 pCmd->NumTxQueues = LE_32(dma->maxNumWCB);
642 637 pCmd->TotalRxWcb = LE_32(1); /* XXX */
643 638 pCmd->RxPdWrPtr = LE_32(dma->rxDescRead);
644 639 /*
645 640 * pCmd->Flags = LE_32(SET_HW_SPEC_HOSTFORM_BEACON
646 641 * #ifdef MWL_HOST_PS_SUPPORT
647 642 * | SET_HW_SPEC_HOST_POWERSAVE
648 643 * #endif
649 644 * | SET_HW_SPEC_HOSTFORM_PROBERESP);
650 645 */
651 646 pCmd->Flags = 0;
652 647 /* disable multi-bss operation for A1-A4 parts */
653 648 if (sc->sc_revs.mh_macRev < 5)
654 649 pCmd->Flags |= LE_32(SET_HW_SPEC_DISABLEMBSS);
655 650
656 651 retval = mwlExecuteCmd(sc, HostCmd_CMD_SET_HW_SPEC);
657 652 if (retval == 0) {
658 653 if (pCmd->Flags & LE_32(SET_HW_SPEC_DISABLEMBSS))
659 654 sc->sc_hw_flags &= ~MHF_MBSS;
660 655 else
661 656 sc->sc_hw_flags |= MHF_MBSS;
662 657 }
663 658
664 659 return (retval);
665 660 }
666 661
667 662 /*
668 663 * Inform firmware of our tx/rx dma setup. The BAR 0
669 664 * writes below are for compatibility with older firmware.
670 665 * For current firmware we send this information with a
671 666 * cmd block via mwl_hal_sethwdma.
672 667 */
673 668 static int
674 669 mwl_setupdma(struct mwl_softc *sc)
675 670 {
676 671 int i, err;
677 672
678 673 sc->sc_hwdma.rxDescRead = sc->sc_rxring.physaddr;
679 674 mwl_mem_write4(sc, sc->sc_hwspecs.rxDescRead, sc->sc_hwdma.rxDescRead);
680 675 mwl_mem_write4(sc, sc->sc_hwspecs.rxDescWrite, sc->sc_hwdma.rxDescRead);
681 676
682 677 for (i = 0; i < MWL_NUM_TX_QUEUES - MWL_NUM_ACK_QUEUES; i++) {
683 678 struct mwl_tx_ring *txring = &sc->sc_txring[i];
684 679 sc->sc_hwdma.wcbBase[i] = txring->physaddr;
685 680 mwl_mem_write4(sc, sc->sc_hwspecs.wcbBase[i],
686 681 sc->sc_hwdma.wcbBase[i]);
687 682 }
688 683 sc->sc_hwdma.maxNumTxWcb = MWL_TX_RING_COUNT;
689 684 sc->sc_hwdma.maxNumWCB = MWL_NUM_TX_QUEUES - MWL_NUM_ACK_QUEUES;
690 685
691 686 err = mwl_hal_sethwdma(sc, &sc->sc_hwdma);
692 687 if (err != 0) {
693 688 MWL_DBG(MWL_DBG_DMA, "mwl: mwl_setupdma(): "
694 689 "unable to setup tx/rx dma; hal status %u\n", err);
695 690 /* XXX */
696 691 }
697 692
698 693 return (err);
699 694 }
700 695
701 696 /* ARGSUSED */
702 697 static void
703 698 mwl_txq_init(struct mwl_softc *sc, struct mwl_tx_ring *txring, int qnum)
704 699 {
705 700 struct mwl_txbuf *bf;
706 701 struct mwl_txdesc *ds;
707 702 int i;
708 703
709 704 txring->qnum = qnum;
710 705 txring->txpri = 0; /* XXX */
711 706
712 707 bf = txring->buf;
713 708 ds = txring->desc;
714 709 for (i = 0; i < MWL_TX_RING_COUNT - 1; i++) {
715 710 bf++;
716 711 ds->pPhysNext = bf->bf_daddr;
717 712 ds++;
718 713 }
719 714 bf = txring->buf;
720 715 ds->pPhysNext = LE_32(bf->bf_daddr);
721 716 }
722 717
723 718 /*
724 719 * Setup a hardware data transmit queue for the specified
725 720 * access control. We record the mapping from ac's
726 721 * to h/w queues for use by mwl_tx_start.
727 722 */
728 723 static int
729 724 mwl_tx_setup(struct mwl_softc *sc, int ac, int mvtype)
730 725 {
731 726 #define N(a) (sizeof (a)/sizeof (a[0]))
732 727 struct mwl_tx_ring *txring;
733 728
734 729 if (ac >= N(sc->sc_ac2q)) {
735 730 MWL_DBG(MWL_DBG_DMA, "mwl: mwl_tx_setup(): "
736 731 "AC %u out of range, max %u!\n",
737 732 ac, (uint_t)N(sc->sc_ac2q));
738 733 return (0);
739 734 }
740 735 if (mvtype >= MWL_NUM_TX_QUEUES) {
741 736 MWL_DBG(MWL_DBG_DMA, "mwl: mwl_tx_setup(): "
742 737 "mvtype %u out of range, max %u!\n",
743 738 mvtype, MWL_NUM_TX_QUEUES);
744 739 return (0);
745 740 }
746 741 txring = &sc->sc_txring[mvtype];
747 742 mwl_txq_init(sc, txring, mvtype);
748 743 sc->sc_ac2q[ac] = txring;
749 744 return (1);
750 745 #undef N
751 746 }
752 747
753 748 static int
754 749 mwl_setup_txq(struct mwl_softc *sc)
755 750 {
756 751 int err = 0;
757 752
758 753 /* NB: insure BK queue is the lowest priority h/w queue */
759 754 if (!mwl_tx_setup(sc, WME_AC_BK, MWL_WME_AC_BK)) {
760 755 MWL_DBG(MWL_DBG_DMA, "mwl: mwl_setup_txq(): "
761 756 "unable to setup xmit queue for %s traffic!\n",
762 757 mwl_wme_acnames[WME_AC_BK]);
763 758 err = EIO;
764 759 return (err);
765 760 }
766 761 if (!mwl_tx_setup(sc, WME_AC_BE, MWL_WME_AC_BE) ||
767 762 !mwl_tx_setup(sc, WME_AC_VI, MWL_WME_AC_VI) ||
768 763 !mwl_tx_setup(sc, WME_AC_VO, MWL_WME_AC_VO)) {
769 764 /*
770 765 * Not enough hardware tx queues to properly do WME;
771 766 * just punt and assign them all to the same h/w queue.
772 767 * We could do a better job of this if, for example,
773 768 * we allocate queues when we switch from station to
774 769 * AP mode.
775 770 */
776 771 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK];
777 772 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK];
778 773 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK];
779 774 }
780 775
781 776 return (err);
782 777 }
783 778
784 779 /*
785 780 * find mwl firmware module's "_start" "_end" symbols
786 781 * and get its size.
787 782 */
788 783 static int
789 784 mwl_loadsym(ddi_modhandle_t modp, char *sym, char **start, size_t *len)
790 785 {
791 786 char start_sym[64];
792 787 char end_sym[64];
793 788 char *p, *end;
794 789 int rv;
795 790 size_t n;
796 791
797 792 (void) snprintf(start_sym, sizeof (start_sym), "%s_start", sym);
798 793 (void) snprintf(end_sym, sizeof (end_sym), "%s_end", sym);
799 794
800 795 p = (char *)ddi_modsym(modp, start_sym, &rv);
801 796 if (p == NULL || rv != 0) {
802 797 MWL_DBG(MWL_DBG_FW, "mwl: mwl_loadsym(): "
803 798 "mod %s: symbol %s not found\n", sym, start_sym);
804 799 return (-1);
805 800 }
806 801
807 802 end = (char *)ddi_modsym(modp, end_sym, &rv);
808 803 if (end == NULL || rv != 0) {
809 804 MWL_DBG(MWL_DBG_FW, "mwl: mwl_loadsym(): "
810 805 "mod %s: symbol %s not found\n", sym, end_sym);
811 806 return (-1);
812 807 }
813 808
814 809 n = _PTRDIFF(end, p);
815 810 *start = p;
816 811 *len = n;
817 812
818 813 return (0);
819 814 }
820 815
821 816 static void
822 817 mwlFwReset(struct mwl_softc *sc)
823 818 {
824 819 if (mwl_ctl_read4(sc, MACREG_REG_INT_CODE) == 0xffffffff) {
825 820 MWL_DBG(MWL_DBG_FW, "mwl: mwlFWReset(): "
826 821 "device not present!\n");
827 822 return;
828 823 }
829 824
830 825 mwl_ctl_write4(sc, MACREG_REG_H2A_INTERRUPT_EVENTS, ISR_RESET);
831 826 sc->sc_hw_flags &= ~MHF_FWHANG;
832 827 }
833 828
834 829 static void
835 830 mwlPokeSdramController(struct mwl_softc *sc, int SDRAMSIZE_Addr)
836 831 {
837 832 /* Set up sdram controller for superflyv2 */
838 833 mwl_ctl_write4(sc, 0x00006014, 0x33);
839 834 mwl_ctl_write4(sc, 0x00006018, 0xa3a2632);
840 835 mwl_ctl_write4(sc, 0x00006010, SDRAMSIZE_Addr);
841 836 }
842 837
843 838 static void
844 839 mwlTriggerPciCmd(struct mwl_softc *sc)
845 840 {
846 841 (void) ddi_dma_sync(sc->sc_cmd_dma.dma_hdl,
847 842 0,
848 843 sc->sc_cmd_dma.alength,
849 844 DDI_DMA_SYNC_FORDEV);
850 845
851 846 mwl_ctl_write4(sc, MACREG_REG_GEN_PTR, sc->sc_cmd_dmaaddr);
852 847 (void) mwl_ctl_read4(sc, MACREG_REG_INT_CODE);
853 848
854 849 mwl_ctl_write4(sc, MACREG_REG_INT_CODE, 0x00);
855 850 (void) mwl_ctl_read4(sc, MACREG_REG_INT_CODE);
856 851
857 852 mwl_ctl_write4(sc, MACREG_REG_H2A_INTERRUPT_EVENTS,
858 853 MACREG_H2ARIC_BIT_DOOR_BELL);
859 854 (void) mwl_ctl_read4(sc, MACREG_REG_INT_CODE);
860 855 }
861 856
862 857 static int
863 858 mwlWaitFor(struct mwl_softc *sc, uint32_t val)
864 859 {
865 860 int i;
866 861
867 862 for (i = 0; i < FW_MAX_NUM_CHECKS; i++) {
868 863 DELAY(FW_CHECK_USECS);
869 864 if (mwl_ctl_read4(sc, MACREG_REG_INT_CODE) == val)
870 865 return (1);
871 866 }
872 867 return (0);
873 868 }
874 869
875 870 /*
876 871 * Firmware block xmit when talking to the boot-rom.
877 872 */
878 873 static int
879 874 mwlSendBlock(struct mwl_softc *sc, int bsize, const void *data, size_t dsize)
880 875 {
881 876 sc->sc_cmd_mem[0] = LE_16(HostCmd_CMD_CODE_DNLD);
882 877 sc->sc_cmd_mem[1] = LE_16(bsize);
883 878 (void) memcpy(&sc->sc_cmd_mem[4], data, dsize);
884 879 mwlTriggerPciCmd(sc);
885 880 /* XXX 2000 vs 200 */
886 881 if (mwlWaitFor(sc, MACREG_INT_CODE_CMD_FINISHED)) {
887 882 mwl_ctl_write4(sc, MACREG_REG_INT_CODE, 0);
888 883 return (1);
889 884 }
890 885
891 886 MWL_DBG(MWL_DBG_FW, "mwl: mwlSendBlock(): "
892 887 "timeout waiting for CMD_FINISHED, INT_CODE 0x%x\n",
893 888 mwl_ctl_read4(sc, MACREG_REG_INT_CODE));
894 889 return (0);
895 890 }
896 891
897 892 /*
898 893 * Firmware block xmit when talking to the 1st-stage loader.
899 894 */
900 895 static int
901 896 mwlSendBlock2(struct mwl_softc *sc, const void *data, size_t dsize)
902 897 {
903 898 (void) memcpy(&sc->sc_cmd_mem[0], data, dsize);
904 899 mwlTriggerPciCmd(sc);
905 900 if (mwlWaitFor(sc, MACREG_INT_CODE_CMD_FINISHED)) {
906 901 mwl_ctl_write4(sc, MACREG_REG_INT_CODE, 0);
907 902 return (1);
908 903 }
909 904
910 905 MWL_DBG(MWL_DBG_FW, "mwl: mwlSendBlock2(): "
911 906 "timeout waiting for CMD_FINISHED, INT_CODE 0x%x\n",
912 907 mwl_ctl_read4(sc, MACREG_REG_INT_CODE));
913 908 return (0);
914 909 }
915 910
916 911 /* ARGSUSED */
917 912 static int
918 913 mwl_fwload(struct mwl_softc *sc, void *fwargs)
919 914 {
920 915 char *fwname = "mwlfw";
921 916 char *fwbootname = "mwlboot";
922 917 char *fwbinname = "mw88W8363fw";
923 918 char *fwboot_index, *fw_index;
924 919 uint8_t *fw, *fwboot;
925 920 ddi_modhandle_t modfw;
926 921 /* XXX get from firmware header */
927 922 uint32_t FwReadySignature = HostCmd_SOFTAP_FWRDY_SIGNATURE;
928 923 uint32_t OpMode = HostCmd_SOFTAP_MODE;
929 924 const uint8_t *fp, *ep;
930 925 size_t fw_size, fwboot_size;
931 926 uint32_t blocksize, nbytes;
932 927 int i, rv, err, ntries;
933 928
934 929 rv = err = 0;
935 930 fw = fwboot = NULL;
936 931 fw_index = fwboot_index = NULL;
937 932
938 933 modfw = ddi_modopen(fwname, KRTLD_MODE_FIRST, &rv);
939 934 if (modfw == NULL) {
940 935 MWL_DBG(MWL_DBG_FW, "mwl: mwl_fwload(): "
941 936 "module %s not found\n", fwname);
942 937 err = -1;
943 938 goto bad2;
944 939 }
945 940
946 941 err = mwl_loadsym(modfw, fwbootname, &fwboot_index, &fwboot_size);
947 942 if (err != 0) {
948 943 MWL_DBG(MWL_DBG_FW, "mwl: mwl_fwload(): "
949 944 "could not get boot firmware\n");
950 945 err = -1;
951 946 goto bad2;
952 947 }
953 948
954 949 err = mwl_loadsym(modfw, fwbinname, &fw_index, &fw_size);
955 950 if (err != 0) {
956 951 MWL_DBG(MWL_DBG_FW, "mwl: mwl_fwload(): "
957 952 "could not get firmware\n");
958 953 err = -1;
959 954 goto bad2;
960 955 }
961 956
962 957 fwboot = (uint8_t *)kmem_alloc(fwboot_size, KM_SLEEP);
963 958 if (fwboot == NULL) {
964 959 MWL_DBG(MWL_DBG_FW, "mwl: mwl_loadfirmware(): "
965 960 "failed to alloc boot firmware memory\n");
966 961 err = -1;
967 962 goto bad2;
968 963 }
969 964 (void) memcpy(fwboot, fwboot_index, fwboot_size);
970 965
971 966 fw = (uint8_t *)kmem_alloc(fw_size, KM_SLEEP);
972 967 if (fw == NULL) {
973 968 MWL_DBG(MWL_DBG_FW, "mwl: mwl_loadfirmware(): "
974 969 "failed to alloc firmware memory\n");
975 970 err = -1;
976 971 goto bad2;
977 972 }
978 973 (void) memcpy(fw, fw_index, fw_size);
979 974
980 975 if (modfw != NULL)
981 976 (void) ddi_modclose(modfw);
982 977
983 978 if (fw_size < 4) {
984 979 MWL_DBG(MWL_DBG_FW, "mwl: mwl_fwload(): "
985 980 "could not load firmware image %s\n",
986 981 fwname);
987 982 err = ENXIO;
988 983 goto bad2;
989 984 }
990 985
991 986 if (fw[0] == 0x01 && fw[1] == 0x00 &&
992 987 fw[2] == 0x00 && fw[3] == 0x00) {
993 988 /*
994 989 * 2-stage load, get the boot firmware.
995 990 */
996 991 if (fwboot == NULL) {
997 992 MWL_DBG(MWL_DBG_FW, "mwl: mwl_fwload(): "
998 993 "could not load firmware image %s\n",
999 994 fwbootname);
1000 995 err = ENXIO;
1001 996 goto bad2;
1002 997 }
1003 998 } else
1004 999 fwboot = NULL;
1005 1000
1006 1001 mwlFwReset(sc);
1007 1002
1008 1003 mwl_ctl_write4(sc, MACREG_REG_A2H_INTERRUPT_CLEAR_SEL,
1009 1004 MACREG_A2HRIC_BIT_MASK);
1010 1005 mwl_ctl_write4(sc, MACREG_REG_A2H_INTERRUPT_CAUSE, 0x00);
1011 1006 mwl_ctl_write4(sc, MACREG_REG_A2H_INTERRUPT_MASK, 0x00);
1012 1007 mwl_ctl_write4(sc, MACREG_REG_A2H_INTERRUPT_STATUS_MASK,
1013 1008 MACREG_A2HRIC_BIT_MASK);
1014 1009 if (sc->sc_SDRAMSIZE_Addr != 0) {
1015 1010 /* Set up sdram controller for superflyv2 */
1016 1011 mwlPokeSdramController(sc, sc->sc_SDRAMSIZE_Addr);
1017 1012 }
1018 1013
1019 1014 MWL_DBG(MWL_DBG_FW, "mwl: mwl_fwload(): "
1020 1015 "load %s firmware image (%u bytes)\n",
1021 1016 fwname, (unsigned int)fw_size);
1022 1017
1023 1018 if (fwboot != NULL) {
1024 1019 /*
1025 1020 * Do 2-stage load. The 1st stage loader is setup
1026 1021 * with the bootrom loader then we load the real
1027 1022 * image using a different handshake. With this
1028 1023 * mechanism the firmware is segmented into chunks
1029 1024 * that have a CRC. If a chunk is incorrect we'll
1030 1025 * be told to retransmit.
1031 1026 */
1032 1027 /* XXX assumes hlpimage fits in a block */
1033 1028 /* NB: zero size block indicates download is finished */
1034 1029 if (!mwlSendBlock(sc, fwboot_size, fwboot, fwboot_size) ||
1035 1030 !mwlSendBlock(sc, 0, NULL, 0)) {
1036 1031 err = ETIMEDOUT;
1037 1032 goto bad;
1038 1033 }
1039 1034 DELAY(200 * FW_CHECK_USECS);
1040 1035 if (sc->sc_SDRAMSIZE_Addr != 0) {
1041 1036 /* Set up sdram controller for superflyv2 */
1042 1037 mwlPokeSdramController(sc, sc->sc_SDRAMSIZE_Addr);
1043 1038 }
1044 1039 nbytes = ntries = 0; /* NB: silence compiler */
1045 1040 for (fp = fw, ep = fp + fw_size; fp < ep; ) {
1046 1041 mwl_ctl_write4(sc, MACREG_REG_INT_CODE, 0);
1047 1042 blocksize = mwl_ctl_read4(sc, MACREG_REG_SCRATCH);
1048 1043 if (blocksize == 0) /* download complete */
1049 1044 break;
1050 1045 if (blocksize > 0x00000c00) {
1051 1046 err = EINVAL;
1052 1047 goto bad;
1053 1048 }
1054 1049 if ((blocksize & 0x1) == 0) {
1055 1050 /* block successfully downloaded, advance */
1056 1051 fp += nbytes;
1057 1052 ntries = 0;
1058 1053 } else {
1059 1054 if (++ntries > 2) {
1060 1055 /*
1061 1056 * Guard against f/w telling us to
1062 1057 * retry infinitely.
1063 1058 */
1064 1059 err = ELOOP;
1065 1060 goto bad;
1066 1061 }
1067 1062 /* clear NAK bit/flag */
1068 1063 blocksize &= ~0x1;
1069 1064 }
1070 1065 if (blocksize > _PTRDIFF(ep, fp)) {
1071 1066 /* XXX this should not happen, what to do? */
1072 1067 blocksize = _PTRDIFF(ep, fp);
1073 1068 }
1074 1069 nbytes = blocksize;
1075 1070 if (!mwlSendBlock2(sc, fp, nbytes)) {
1076 1071 err = ETIMEDOUT;
1077 1072 goto bad;
1078 1073 }
1079 1074 }
1080 1075 } else {
1081 1076 for (fp = fw, ep = fp + fw_size; fp < ep; ) {
1082 1077 nbytes = _PTRDIFF(ep, fp);
1083 1078 if (nbytes > FW_DOWNLOAD_BLOCK_SIZE)
1084 1079 nbytes = FW_DOWNLOAD_BLOCK_SIZE;
1085 1080 if (!mwlSendBlock(sc, FW_DOWNLOAD_BLOCK_SIZE, fp,
1086 1081 nbytes)) {
1087 1082 err = EIO;
1088 1083 goto bad;
1089 1084 }
1090 1085 fp += nbytes;
1091 1086 }
1092 1087 }
1093 1088
1094 1089 /*
1095 1090 * Wait for firmware to startup; we monitor the
1096 1091 * INT_CODE register waiting for a signature to
1097 1092 * written back indicating it's ready to go.
1098 1093 */
1099 1094 sc->sc_cmd_mem[1] = 0;
1100 1095 /*
1101 1096 * XXX WAR for mfg fw download
1102 1097 */
1103 1098 if (OpMode != HostCmd_STA_MODE)
1104 1099 mwlTriggerPciCmd(sc);
1105 1100 for (i = 0; i < FW_MAX_NUM_CHECKS; i++) {
1106 1101 mwl_ctl_write4(sc, MACREG_REG_GEN_PTR, OpMode);
1107 1102 DELAY(FW_CHECK_USECS);
1108 1103 if (mwl_ctl_read4(sc, MACREG_REG_INT_CODE) ==
1109 1104 FwReadySignature) {
1110 1105 mwl_ctl_write4(sc, MACREG_REG_INT_CODE, 0x00);
1111 1106 return (mwlResetHalState(sc));
1112 1107 }
1113 1108 }
1114 1109 MWL_DBG(MWL_DBG_FW, "mwl: mwl_fwload(): "
1115 1110 "firmware download timeout\n");
1116 1111 return (ETIMEDOUT);
1117 1112 bad:
1118 1113 mwlFwReset(sc);
1119 1114 bad2:
1120 1115 if (fw != NULL)
1121 1116 kmem_free(fw, fw_size);
1122 1117 if (fwboot != NULL)
1123 1118 kmem_free(fwboot, fwboot_size);
1124 1119 fwboot = fw = NULL;
1125 1120 fwboot_index = fw_index = NULL;
1126 1121 if (modfw != NULL)
1127 1122 (void) ddi_modclose(modfw);
1128 1123 return (err);
1129 1124 }
1130 1125
1131 1126 /*
1132 1127 * Low level firmware cmd block handshake support.
1133 1128 */
1134 1129 static void
1135 1130 mwlSendCmd(struct mwl_softc *sc)
1136 1131 {
1137 1132 (void) ddi_dma_sync(sc->sc_cmd_dma.dma_hdl,
1138 1133 0,
1139 1134 sc->sc_cmd_dma.alength,
1140 1135 DDI_DMA_SYNC_FORDEV);
1141 1136
1142 1137 mwl_ctl_write4(sc, MACREG_REG_GEN_PTR, sc->sc_cmd_dmaaddr);
1143 1138 (void) mwl_ctl_read4(sc, MACREG_REG_INT_CODE);
1144 1139
1145 1140 mwl_ctl_write4(sc, MACREG_REG_H2A_INTERRUPT_EVENTS,
1146 1141 MACREG_H2ARIC_BIT_DOOR_BELL);
1147 1142 }
1148 1143
1149 1144 static int
1150 1145 mwlExecuteCmd(struct mwl_softc *sc, unsigned short cmd)
1151 1146 {
1152 1147 if (mwl_ctl_read4(sc, MACREG_REG_INT_CODE) == 0xffffffff) {
1153 1148 MWL_DBG(MWL_DBG_CMD, "mwl: mwlExecuteCmd(): "
1154 1149 "device not present!\n");
1155 1150 return (EIO);
1156 1151 }
1157 1152 mwlSendCmd(sc);
1158 1153 if (!mwlWaitForCmdComplete(sc, 0x8000 | cmd)) {
1159 1154 MWL_DBG(MWL_DBG_CMD, "mwl: mwlExecuteCmd(): "
1160 1155 "timeout waiting for f/w cmd %s\n", mwlcmdname(cmd));
1161 1156 return (ETIMEDOUT);
1162 1157 }
1163 1158 (void) ddi_dma_sync(sc->sc_cmd_dma.dma_hdl,
1164 1159 0,
1165 1160 sc->sc_cmd_dma.alength,
1166 1161 DDI_DMA_SYNC_FORDEV);
1167 1162
1168 1163 MWL_DBG(MWL_DBG_CMD, "mwl: mwlExecuteCmd(): "
1169 1164 "send cmd %s\n", mwlcmdname(cmd));
1170 1165
1171 1166 if (mwl_dbg_flags & MWL_DBG_CMD)
1172 1167 dumpresult(sc, 1);
1173 1168
1174 1169 return (0);
1175 1170 }
1176 1171
1177 1172 static int
1178 1173 mwlWaitForCmdComplete(struct mwl_softc *sc, uint16_t cmdCode)
1179 1174 {
1180 1175 #define MAX_WAIT_FW_COMPLETE_ITERATIONS 10000
1181 1176 int i;
1182 1177
1183 1178 for (i = 0; i < MAX_WAIT_FW_COMPLETE_ITERATIONS; i++) {
1184 1179 if (sc->sc_cmd_mem[0] == LE_16(cmdCode))
1185 1180 return (1);
1186 1181 DELAY(1 * 1000);
1187 1182 }
1188 1183 return (0);
1189 1184 #undef MAX_WAIT_FW_COMPLETE_ITERATIONS
1190 1185 }
1191 1186
1192 1187 static const char *
1193 1188 mwlcmdname(int cmd)
1194 1189 {
1195 1190 static char buf[12];
1196 1191 #define CMD(x) case HostCmd_CMD_##x: return #x
1197 1192 switch (cmd) {
1198 1193 CMD(CODE_DNLD);
1199 1194 CMD(GET_HW_SPEC);
1200 1195 CMD(SET_HW_SPEC);
1201 1196 CMD(MAC_MULTICAST_ADR);
1202 1197 CMD(802_11_GET_STAT);
1203 1198 CMD(MAC_REG_ACCESS);
1204 1199 CMD(BBP_REG_ACCESS);
1205 1200 CMD(RF_REG_ACCESS);
1206 1201 CMD(802_11_RADIO_CONTROL);
1207 1202 CMD(802_11_RF_TX_POWER);
1208 1203 CMD(802_11_RF_ANTENNA);
1209 1204 CMD(SET_BEACON);
1210 1205 CMD(SET_RF_CHANNEL);
1211 1206 CMD(SET_AID);
1212 1207 CMD(SET_INFRA_MODE);
1213 1208 CMD(SET_G_PROTECT_FLAG);
1214 1209 CMD(802_11_RTS_THSD);
1215 1210 CMD(802_11_SET_SLOT);
1216 1211 CMD(SET_EDCA_PARAMS);
1217 1212 CMD(802_11H_DETECT_RADAR);
1218 1213 CMD(SET_WMM_MODE);
1219 1214 CMD(HT_GUARD_INTERVAL);
1220 1215 CMD(SET_FIXED_RATE);
1221 1216 CMD(SET_LINKADAPT_CS_MODE);
1222 1217 CMD(SET_MAC_ADDR);
1223 1218 CMD(SET_RATE_ADAPT_MODE);
1224 1219 CMD(BSS_START);
1225 1220 CMD(SET_NEW_STN);
1226 1221 CMD(SET_KEEP_ALIVE);
1227 1222 CMD(SET_APMODE);
1228 1223 CMD(SET_SWITCH_CHANNEL);
1229 1224 CMD(UPDATE_ENCRYPTION);
1230 1225 CMD(BASTREAM);
1231 1226 CMD(SET_RIFS);
1232 1227 CMD(SET_N_PROTECT_FLAG);
1233 1228 CMD(SET_N_PROTECT_OPMODE);
1234 1229 CMD(SET_OPTIMIZATION_LEVEL);
1235 1230 CMD(GET_CALTABLE);
1236 1231 CMD(SET_MIMOPSHT);
1237 1232 CMD(GET_BEACON);
1238 1233 CMD(SET_REGION_CODE);
1239 1234 CMD(SET_POWERSAVESTATION);
1240 1235 CMD(SET_TIM);
1241 1236 CMD(GET_TIM);
1242 1237 CMD(GET_SEQNO);
1243 1238 CMD(DWDS_ENABLE);
1244 1239 CMD(AMPDU_RETRY_RATEDROP_MODE);
1245 1240 CMD(CFEND_ENABLE);
1246 1241 }
1247 1242 (void) snprintf(buf, sizeof (buf), "0x%x", cmd);
1248 1243 return (buf);
1249 1244 #undef CMD
1250 1245 }
1251 1246
1252 1247 static void
1253 1248 dumpresult(struct mwl_softc *sc, int showresult)
1254 1249 {
1255 1250 const FWCmdHdr *h = (const FWCmdHdr *)sc->sc_cmd_mem;
1256 1251 int len;
1257 1252
1258 1253 len = LE_16(h->Length);
1259 1254 #ifdef MWL_MBSS_SUPPORT
1260 1255 MWL_DBG(MWL_DBG_CMD, "mwl: mwl_dumpresult(): "
1261 1256 "Cmd %s Length %d SeqNum %d MacId %d",
1262 1257 mwlcmdname(LE_16(h->Cmd) & ~0x8000), len, h->SeqNum, h->MacId);
1263 1258 #else
1264 1259 MWL_DBG(MWL_DBG_CMD, "mwl: mwl_dumpresult(): "
1265 1260 "Cmd %s Length %d SeqNum %d",
1266 1261 mwlcmdname(LE_16(h->Cmd) & ~0x8000), len, LE_16(h->SeqNum));
1267 1262 #endif
1268 1263 if (showresult) {
1269 1264 const char *results[] =
1270 1265 { "OK", "ERROR", "NOT_SUPPORT", "PENDING", "BUSY",
1271 1266 "PARTIAL_DATA" };
1272 1267 int result = LE_16(h->Result);
1273 1268
1274 1269 if (result <= HostCmd_RESULT_PARTIAL_DATA)
1275 1270 MWL_DBG(MWL_DBG_CMD, "mwl: dumpresult(): "
1276 1271 "Result %s", results[result]);
1277 1272 else
1278 1273 MWL_DBG(MWL_DBG_CMD, "mwl: dumpresult(): "
1279 1274 "Result %d", result);
1280 1275 }
1281 1276 }
1282 1277
1283 1278 static int
1284 1279 mwlGetCalTable(struct mwl_softc *sc, uint8_t annex, uint8_t index)
1285 1280 {
1286 1281 HostCmd_FW_GET_CALTABLE *pCmd;
1287 1282 int retval;
1288 1283
1289 1284 _CMD_SETUP(pCmd, HostCmd_FW_GET_CALTABLE, HostCmd_CMD_GET_CALTABLE);
1290 1285 pCmd->annex = annex;
1291 1286 pCmd->index = index;
1292 1287 (void) memset(pCmd->calTbl, 0, sizeof (pCmd->calTbl));
1293 1288
1294 1289 retval = mwlExecuteCmd(sc, HostCmd_CMD_GET_CALTABLE);
1295 1290 if (retval == 0 &&
1296 1291 pCmd->calTbl[0] != annex && annex != 0 && annex != 255)
1297 1292 retval = EIO;
1298 1293 return (retval);
1299 1294 }
1300 1295
1301 1296 /*
1302 1297 * Construct channel info for 2.4GHz channels from cal data.
1303 1298 */
1304 1299 static void
1305 1300 get2Ghz(MWL_HAL_CHANNELINFO *ci, const uint8_t table[], int len)
1306 1301 {
1307 1302 int i, j;
1308 1303
1309 1304 j = 0;
1310 1305 for (i = 0; i < len; i += 4) {
1311 1306 struct mwl_hal_channel *hc = &ci->channels[j];
1312 1307 hc->ieee = 1+j;
1313 1308 hc->freq = ieee2mhz(1+j);
1314 1309 (void) memcpy(hc->targetPowers, &table[i], 4);
1315 1310 setmaxtxpow(hc, 0, 4);
1316 1311 j++;
1317 1312 }
1318 1313 ci->nchannels = j;
1319 1314 ci->freqLow = ieee2mhz(1);
1320 1315 ci->freqHigh = ieee2mhz(j);
1321 1316 }
1322 1317
1323 1318 /*
1324 1319 * Construct channel info for 5GHz channels from cal data.
1325 1320 */
1326 1321 static void
1327 1322 get5Ghz(MWL_HAL_CHANNELINFO *ci, const uint8_t table[], int len)
1328 1323 {
1329 1324 int i, j, f, l, h;
1330 1325
1331 1326 l = 32000;
1332 1327 h = 0;
1333 1328 j = 0;
1334 1329 for (i = 0; i < len; i += 4) {
1335 1330 struct mwl_hal_channel *hc;
1336 1331
1337 1332 if (table[i] == 0)
1338 1333 continue;
1339 1334 f = 5000 + 5*table[i];
1340 1335 if (f < l)
1341 1336 l = f;
1342 1337 if (f > h)
1343 1338 h = f;
1344 1339 hc = &ci->channels[j];
1345 1340 hc->freq = (uint16_t)f;
1346 1341 hc->ieee = table[i];
1347 1342 (void) memcpy(hc->targetPowers, &table[i], 4);
1348 1343 setmaxtxpow(hc, 1, 4); /* NB: col 1 is the freq, skip */
1349 1344 j++;
1350 1345 }
1351 1346 ci->nchannels = j;
1352 1347 ci->freqLow = (uint16_t)((l == 32000) ? 0 : l);
1353 1348 ci->freqHigh = (uint16_t)h;
1354 1349 }
1355 1350
1356 1351 /*
1357 1352 * Calculate the max tx power from the channel's cal data.
1358 1353 */
1359 1354 static void
1360 1355 setmaxtxpow(struct mwl_hal_channel *hc, int i, int maxix)
1361 1356 {
1362 1357 hc->maxTxPow = hc->targetPowers[i];
1363 1358 for (i++; i < maxix; i++)
1364 1359 if (hc->targetPowers[i] > hc->maxTxPow)
1365 1360 hc->maxTxPow = hc->targetPowers[i];
1366 1361 }
1367 1362
1368 1363 static uint16_t
1369 1364 ieee2mhz(int chan)
1370 1365 {
1371 1366 if (chan == 14)
1372 1367 return (2484);
1373 1368 if (chan < 14)
1374 1369 return (2407 + chan * 5);
1375 1370 return (2512 + (chan - 15) * 20);
1376 1371 }
1377 1372
1378 1373 static void
1379 1374 dumpcaldata(const char *name, const uint8_t *table, int n)
1380 1375 {
1381 1376 int i;
1382 1377 MWL_DBG(MWL_DBG_HW, "\n%s:\n", name);
1383 1378 for (i = 0; i < n; i += 4)
1384 1379 MWL_DBG(MWL_DBG_HW, "[%2d] %3d %3d %3d %3d\n",
1385 1380 i/4, table[i+0], table[i+1], table[i+2], table[i+3]);
1386 1381 }
1387 1382
1388 1383 static int
1389 1384 mwlGetPwrCalTable(struct mwl_softc *sc)
1390 1385 {
1391 1386 const uint8_t *data;
1392 1387 MWL_HAL_CHANNELINFO *ci;
1393 1388 int len;
1394 1389
1395 1390 /* NB: we hold the lock so it's ok to use cmdbuf */
1396 1391 data = ((const HostCmd_FW_GET_CALTABLE *) sc->sc_cmd_mem)->calTbl;
1397 1392 if (mwlGetCalTable(sc, 33, 0) == 0) {
1398 1393 len = (data[2] | (data[3] << 8)) - 12;
1399 1394 if (len > PWTAGETRATETABLE20M)
1400 1395 len = PWTAGETRATETABLE20M;
1401 1396 dumpcaldata("2.4G 20M", &data[12], len);
1402 1397 get2Ghz(&sc->sc_20M, &data[12], len);
1403 1398 }
1404 1399 if (mwlGetCalTable(sc, 34, 0) == 0) {
1405 1400 len = (data[2] | (data[3] << 8)) - 12;
1406 1401 if (len > PWTAGETRATETABLE40M)
1407 1402 len = PWTAGETRATETABLE40M;
1408 1403 dumpcaldata("2.4G 40M", &data[12], len);
1409 1404 ci = &sc->sc_40M;
1410 1405 get2Ghz(ci, &data[12], len);
1411 1406 }
1412 1407 if (mwlGetCalTable(sc, 35, 0) == 0) {
1413 1408 len = (data[2] | (data[3] << 8)) - 20;
1414 1409 if (len > PWTAGETRATETABLE20M_5G)
1415 1410 len = PWTAGETRATETABLE20M_5G;
1416 1411 dumpcaldata("5G 20M", &data[20], len);
1417 1412 get5Ghz(&sc->sc_20M_5G, &data[20], len);
1418 1413 }
1419 1414 if (mwlGetCalTable(sc, 36, 0) == 0) {
1420 1415 len = (data[2] | (data[3] << 8)) - 20;
1421 1416 if (len > PWTAGETRATETABLE40M_5G)
1422 1417 len = PWTAGETRATETABLE40M_5G;
1423 1418 dumpcaldata("5G 40M", &data[20], len);
1424 1419 ci = &sc->sc_40M_5G;
1425 1420 get5Ghz(ci, &data[20], len);
1426 1421 }
1427 1422 sc->sc_hw_flags |= MHF_CALDATA;
1428 1423 return (0);
1429 1424 }
1430 1425
1431 1426 /*
1432 1427 * Reset internal state after a firmware download.
1433 1428 */
1434 1429 static int
1435 1430 mwlResetHalState(struct mwl_softc *sc)
1436 1431 {
1437 1432 int err = 0;
1438 1433
1439 1434 /*
1440 1435 * Fetch cal data for later use.
1441 1436 * XXX may want to fetch other stuff too.
1442 1437 */
1443 1438 /* XXX check return */
1444 1439 if ((sc->sc_hw_flags & MHF_CALDATA) == 0)
1445 1440 err = mwlGetPwrCalTable(sc);
1446 1441 return (err);
1447 1442 }
1448 1443
1449 1444 #define IEEE80211_CHAN_HTG (IEEE80211_CHAN_HT|IEEE80211_CHAN_G)
1450 1445 #define IEEE80211_CHAN_HTA (IEEE80211_CHAN_HT|IEEE80211_CHAN_A)
1451 1446
1452 1447 static void
1453 1448 addchan(struct mwl_channel *c, int freq, int flags, int ieee, int txpow)
1454 1449 {
1455 1450 c->ic_freq = (uint16_t)freq;
1456 1451 c->ic_flags = flags;
1457 1452 c->ic_ieee = (uint8_t)ieee;
1458 1453 c->ic_minpower = 0;
1459 1454 c->ic_maxpower = 2*txpow;
1460 1455 c->ic_maxregpower = (uint8_t)txpow;
1461 1456 }
1462 1457
1463 1458 static const struct mwl_channel *
1464 1459 findchannel(const struct mwl_channel chans[], int nchans,
1465 1460 int freq, int flags)
1466 1461 {
1467 1462 const struct mwl_channel *c;
1468 1463 int i;
1469 1464
1470 1465 for (i = 0; i < nchans; i++) {
1471 1466 c = &chans[i];
1472 1467 if (c->ic_freq == freq && c->ic_flags == flags)
1473 1468 return (c);
1474 1469 }
1475 1470 return (NULL);
1476 1471 }
1477 1472
1478 1473 static void
1479 1474 addht40channels(struct mwl_channel chans[], int maxchans, int *nchans,
1480 1475 const MWL_HAL_CHANNELINFO *ci, int flags)
1481 1476 {
1482 1477 struct mwl_channel *c;
1483 1478 const struct mwl_channel *extc;
1484 1479 const struct mwl_hal_channel *hc;
1485 1480 int i;
1486 1481
1487 1482 c = &chans[*nchans];
1488 1483
1489 1484 flags &= ~IEEE80211_CHAN_HT;
1490 1485 for (i = 0; i < ci->nchannels; i++) {
1491 1486 /*
1492 1487 * Each entry defines an HT40 channel pair; find the
1493 1488 * extension channel above and the insert the pair.
1494 1489 */
1495 1490 hc = &ci->channels[i];
1496 1491 extc = findchannel(chans, *nchans, hc->freq+20,
1497 1492 flags | IEEE80211_CHAN_HT20);
1498 1493 if (extc != NULL) {
1499 1494 if (*nchans >= maxchans)
1500 1495 break;
1501 1496 addchan(c, hc->freq, flags | IEEE80211_CHAN_HT40U,
1502 1497 hc->ieee, hc->maxTxPow);
1503 1498 c->ic_extieee = extc->ic_ieee;
1504 1499 c++, (*nchans)++;
1505 1500 if (*nchans >= maxchans)
1506 1501 break;
1507 1502 addchan(c, extc->ic_freq, flags | IEEE80211_CHAN_HT40D,
1508 1503 extc->ic_ieee, hc->maxTxPow);
1509 1504 c->ic_extieee = hc->ieee;
1510 1505 c++, (*nchans)++;
1511 1506 }
1512 1507 }
1513 1508 }
1514 1509
1515 1510 static void
1516 1511 addchannels(struct mwl_channel chans[], int maxchans, int *nchans,
1517 1512 const MWL_HAL_CHANNELINFO *ci, int flags)
1518 1513 {
1519 1514 struct mwl_channel *c;
1520 1515 int i;
1521 1516
1522 1517 c = &chans[*nchans];
1523 1518
1524 1519 for (i = 0; i < ci->nchannels; i++) {
1525 1520 const struct mwl_hal_channel *hc;
1526 1521
1527 1522 hc = &ci->channels[i];
1528 1523 if (*nchans >= maxchans)
1529 1524 break;
1530 1525 addchan(c, hc->freq, flags, hc->ieee, hc->maxTxPow);
1531 1526 c++, (*nchans)++;
1532 1527
1533 1528 if (flags == IEEE80211_CHAN_G || flags == IEEE80211_CHAN_HTG) {
1534 1529 /* g channel have a separate b-only entry */
1535 1530 if (*nchans >= maxchans)
1536 1531 break;
1537 1532 c[0] = c[-1];
1538 1533 c[-1].ic_flags = IEEE80211_CHAN_B;
1539 1534 c++, (*nchans)++;
1540 1535 }
1541 1536 if (flags == IEEE80211_CHAN_HTG) {
1542 1537 /* HT g channel have a separate g-only entry */
1543 1538 if (*nchans >= maxchans)
1544 1539 break;
1545 1540 c[-1].ic_flags = IEEE80211_CHAN_G;
1546 1541 c[0] = c[-1];
1547 1542 c[0].ic_flags &= ~IEEE80211_CHAN_HT;
1548 1543 c[0].ic_flags |= IEEE80211_CHAN_HT20; /* HT20 */
1549 1544 c++, (*nchans)++;
1550 1545 }
1551 1546 if (flags == IEEE80211_CHAN_HTA) {
1552 1547 /* HT a channel have a separate a-only entry */
1553 1548 if (*nchans >= maxchans)
1554 1549 break;
1555 1550 c[-1].ic_flags = IEEE80211_CHAN_A;
1556 1551 c[0] = c[-1];
1557 1552 c[0].ic_flags &= ~IEEE80211_CHAN_HT;
1558 1553 c[0].ic_flags |= IEEE80211_CHAN_HT20; /* HT20 */
1559 1554 c++, (*nchans)++;
1560 1555 }
1561 1556 }
1562 1557 }
1563 1558
1564 1559 static int
1565 1560 mwl_hal_getchannelinfo(struct mwl_softc *sc, int band, int chw,
1566 1561 const MWL_HAL_CHANNELINFO **ci)
1567 1562 {
1568 1563 switch (band) {
1569 1564 case MWL_FREQ_BAND_2DOT4GHZ:
1570 1565 *ci = (chw == MWL_CH_20_MHz_WIDTH) ? &sc->sc_20M : &sc->sc_40M;
1571 1566 break;
1572 1567 case MWL_FREQ_BAND_5GHZ:
1573 1568 *ci = (chw == MWL_CH_20_MHz_WIDTH) ?
1574 1569 &sc->sc_20M_5G : &sc->sc_40M_5G;
1575 1570 break;
1576 1571 default:
1577 1572 return (EINVAL);
1578 1573 }
1579 1574 return (((*ci)->freqLow == (*ci)->freqHigh) ? EINVAL : 0);
1580 1575 }
1581 1576
1582 1577 static void
1583 1578 getchannels(struct mwl_softc *sc, int maxchans, int *nchans,
1584 1579 struct mwl_channel chans[])
1585 1580 {
1586 1581 const MWL_HAL_CHANNELINFO *ci;
1587 1582
1588 1583 /*
1589 1584 * Use the channel info from the hal to craft the
1590 1585 * channel list. Note that we pass back an unsorted
1591 1586 * list; the caller is required to sort it for us
1592 1587 * (if desired).
1593 1588 */
1594 1589 *nchans = 0;
1595 1590 if (mwl_hal_getchannelinfo(sc,
1596 1591 MWL_FREQ_BAND_2DOT4GHZ, MWL_CH_20_MHz_WIDTH, &ci) == 0)
1597 1592 addchannels(chans, maxchans, nchans, ci, IEEE80211_CHAN_HTG);
1598 1593 if (mwl_hal_getchannelinfo(sc,
1599 1594 MWL_FREQ_BAND_5GHZ, MWL_CH_20_MHz_WIDTH, &ci) == 0)
1600 1595 addchannels(chans, maxchans, nchans, ci, IEEE80211_CHAN_HTA);
1601 1596 if (mwl_hal_getchannelinfo(sc,
1602 1597 MWL_FREQ_BAND_2DOT4GHZ, MWL_CH_40_MHz_WIDTH, &ci) == 0)
1603 1598 addht40channels(chans, maxchans, nchans, ci,
1604 1599 IEEE80211_CHAN_HTG);
1605 1600 if (mwl_hal_getchannelinfo(sc,
1606 1601 MWL_FREQ_BAND_5GHZ, MWL_CH_40_MHz_WIDTH, &ci) == 0)
1607 1602 addht40channels(chans, maxchans, nchans, ci,
1608 1603 IEEE80211_CHAN_HTA);
1609 1604 }
1610 1605
1611 1606 static int
1612 1607 mwl_getchannels(struct mwl_softc *sc)
1613 1608 {
1614 1609 /*
1615 1610 * Use the channel info from the hal to craft the
1616 1611 * channel list for net80211. Note that we pass up
1617 1612 * an unsorted list; net80211 will sort it for us.
1618 1613 */
1619 1614 (void) memset(sc->sc_channels, 0, sizeof (sc->sc_channels));
1620 1615 sc->sc_nchans = 0;
1621 1616 getchannels(sc, IEEE80211_CHAN_MAX, &sc->sc_nchans, sc->sc_channels);
1622 1617
1623 1618 sc->sc_regdomain.regdomain = SKU_DEBUG;
1624 1619 sc->sc_regdomain.country = CTRY_DEFAULT;
1625 1620 sc->sc_regdomain.location = 'I';
1626 1621 sc->sc_regdomain.isocc[0] = ' '; /* XXX? */
1627 1622 sc->sc_regdomain.isocc[1] = ' ';
1628 1623 return (sc->sc_nchans == 0 ? EIO : 0);
1629 1624 }
1630 1625
1631 1626 #undef IEEE80211_CHAN_HTA
1632 1627 #undef IEEE80211_CHAN_HTG
1633 1628
1634 1629 /*
1635 1630 * Return "hw specs". Note this must be the first
1636 1631 * cmd MUST be done after a firmware download or the
1637 1632 * f/w will lockup.
1638 1633 * XXX move into the hal so driver doesn't need to be responsible
1639 1634 */
1640 1635 static int
1641 1636 mwl_gethwspecs(struct mwl_softc *sc)
1642 1637 {
1643 1638 struct mwl_hal_hwspec *hw;
1644 1639 HostCmd_DS_GET_HW_SPEC *pCmd;
1645 1640 int retval;
1646 1641
1647 1642 hw = &sc->sc_hwspecs;
1648 1643 _CMD_SETUP(pCmd, HostCmd_DS_GET_HW_SPEC, HostCmd_CMD_GET_HW_SPEC);
1649 1644 (void) memset(&pCmd->PermanentAddr[0], 0xff, IEEE80211_ADDR_LEN);
1650 1645 pCmd->ulFwAwakeCookie = LE_32((unsigned int)sc->sc_cmd_dmaaddr + 2048);
1651 1646
1652 1647 retval = mwlExecuteCmd(sc, HostCmd_CMD_GET_HW_SPEC);
1653 1648 if (retval == 0) {
1654 1649 IEEE80211_ADDR_COPY(hw->macAddr, pCmd->PermanentAddr);
1655 1650 hw->wcbBase[0] = LE_32(pCmd->WcbBase0) & 0x0000ffff;
1656 1651 hw->wcbBase[1] = LE_32(pCmd->WcbBase1[0]) & 0x0000ffff;
1657 1652 hw->wcbBase[2] = LE_32(pCmd->WcbBase1[1]) & 0x0000ffff;
1658 1653 hw->wcbBase[3] = LE_32(pCmd->WcbBase1[2]) & 0x0000ffff;
1659 1654 hw->rxDescRead = LE_32(pCmd->RxPdRdPtr)& 0x0000ffff;
1660 1655 hw->rxDescWrite = LE_32(pCmd->RxPdWrPtr)& 0x0000ffff;
1661 1656 hw->regionCode = LE_16(pCmd->RegionCode) & 0x00ff;
1662 1657 hw->fwReleaseNumber = LE_32(pCmd->FWReleaseNumber);
1663 1658 hw->maxNumWCB = LE_16(pCmd->NumOfWCB);
1664 1659 hw->maxNumMCAddr = LE_16(pCmd->NumOfMCastAddr);
1665 1660 hw->numAntennas = LE_16(pCmd->NumberOfAntenna);
1666 1661 hw->hwVersion = pCmd->Version;
1667 1662 hw->hostInterface = pCmd->HostIf;
1668 1663
1669 1664 sc->sc_revs.mh_macRev = hw->hwVersion; /* XXX */
1670 1665 sc->sc_revs.mh_phyRev = hw->hostInterface; /* XXX */
1671 1666 }
1672 1667
1673 1668 return (retval);
1674 1669 }
1675 1670
1676 1671 static int
1677 1672 mwl_hal_setmac_locked(struct mwl_softc *sc,
1678 1673 const uint8_t addr[IEEE80211_ADDR_LEN])
1679 1674 {
1680 1675 HostCmd_DS_SET_MAC *pCmd;
1681 1676
1682 1677 _VCMD_SETUP(pCmd, HostCmd_DS_SET_MAC, HostCmd_CMD_SET_MAC_ADDR);
1683 1678 IEEE80211_ADDR_COPY(&pCmd->MacAddr[0], addr);
1684 1679 #ifdef MWL_MBSS_SUPPORT
1685 1680 /* NB: already byte swapped */
1686 1681 pCmd->MacType = WL_MAC_TYPE_PRIMARY_CLIENT;
1687 1682 #endif
1688 1683 return (mwlExecuteCmd(sc, HostCmd_CMD_SET_MAC_ADDR));
1689 1684 }
1690 1685
1691 1686 static void
1692 1687 cvtPeerInfo(PeerInfo_t *to, const MWL_HAL_PEERINFO *from)
1693 1688 {
1694 1689 to->LegacyRateBitMap = LE_32(from->LegacyRateBitMap);
1695 1690 to->HTRateBitMap = LE_32(from->HTRateBitMap);
1696 1691 to->CapInfo = LE_16(from->CapInfo);
1697 1692 to->HTCapabilitiesInfo = LE_16(from->HTCapabilitiesInfo);
1698 1693 to->MacHTParamInfo = from->MacHTParamInfo;
1699 1694 to->AddHtInfo.ControlChan = from->AddHtInfo.ControlChan;
1700 1695 to->AddHtInfo.AddChan = from->AddHtInfo.AddChan;
1701 1696 to->AddHtInfo.OpMode = LE_16(from->AddHtInfo.OpMode);
1702 1697 to->AddHtInfo.stbc = LE_16(from->AddHtInfo.stbc);
1703 1698 }
1704 1699
1705 1700 /* XXX station id must be in [0..63] */
1706 1701 static int
1707 1702 mwl_hal_newstation(struct mwl_softc *sc,
1708 1703 const uint8_t addr[IEEE80211_ADDR_LEN], uint16_t aid, uint16_t sid,
1709 1704 const MWL_HAL_PEERINFO *peer, int isQosSta, int wmeInfo)
1710 1705 {
1711 1706 HostCmd_FW_SET_NEW_STN *pCmd;
1712 1707 int retval;
1713 1708
1714 1709 _VCMD_SETUP(pCmd, HostCmd_FW_SET_NEW_STN, HostCmd_CMD_SET_NEW_STN);
1715 1710 pCmd->AID = LE_16(aid);
1716 1711 pCmd->StnId = LE_16(sid);
1717 1712 pCmd->Action = LE_16(0); /* SET */
1718 1713 if (peer != NULL) {
1719 1714 /* NB: must fix up byte order */
1720 1715 cvtPeerInfo(&pCmd->PeerInfo, peer);
1721 1716 }
1722 1717 IEEE80211_ADDR_COPY(&pCmd->MacAddr[0], addr);
1723 1718 pCmd->Qosinfo = (uint8_t)wmeInfo;
1724 1719 pCmd->isQosSta = (isQosSta != 0);
1725 1720
1726 1721 MWL_DBG(MWL_DBG_HW, "mwl: mwl_hal_newstation(): "
1727 1722 "LegacyRateBitMap %x, CapInfo %x\n",
1728 1723 pCmd->PeerInfo.LegacyRateBitMap, pCmd->PeerInfo.CapInfo);
1729 1724
1730 1725 retval = mwlExecuteCmd(sc, HostCmd_CMD_SET_NEW_STN);
1731 1726 return (retval);
1732 1727 }
1733 1728
1734 1729 /*
1735 1730 * Configure antenna use.
1736 1731 * Takes effect immediately.
1737 1732 * XXX tx antenna setting ignored
1738 1733 * XXX rx antenna setting should always be 3 (for now)
1739 1734 */
1740 1735 static int
1741 1736 mwl_hal_setantenna(struct mwl_softc *sc, MWL_HAL_ANTENNA dirSet, int ant)
1742 1737 {
1743 1738 HostCmd_DS_802_11_RF_ANTENNA *pCmd;
1744 1739 int retval;
1745 1740
1746 1741 if (!(dirSet == WL_ANTENNATYPE_RX || dirSet == WL_ANTENNATYPE_TX))
1747 1742 return (EINVAL);
1748 1743
1749 1744 _CMD_SETUP(pCmd, HostCmd_DS_802_11_RF_ANTENNA,
1750 1745 HostCmd_CMD_802_11_RF_ANTENNA);
1751 1746 pCmd->Action = LE_16(dirSet);
1752 1747 if (ant == 0) /* default to all/both antennae */
1753 1748 ant = 3;
1754 1749 pCmd->AntennaMode = LE_16(ant);
1755 1750
1756 1751 retval = mwlExecuteCmd(sc, HostCmd_CMD_802_11_RF_ANTENNA);
1757 1752 return (retval);
1758 1753 }
1759 1754
1760 1755 /*
1761 1756 * Configure radio.
1762 1757 * Takes effect immediately.
1763 1758 * XXX preamble installed after set fixed rate cmd
1764 1759 */
1765 1760 static int
1766 1761 mwl_hal_setradio(struct mwl_softc *sc, int onoff, MWL_HAL_PREAMBLE preamble)
1767 1762 {
1768 1763 HostCmd_DS_802_11_RADIO_CONTROL *pCmd;
1769 1764 int retval;
1770 1765
1771 1766 _CMD_SETUP(pCmd, HostCmd_DS_802_11_RADIO_CONTROL,
1772 1767 HostCmd_CMD_802_11_RADIO_CONTROL);
1773 1768 pCmd->Action = LE_16(HostCmd_ACT_GEN_SET);
1774 1769 if (onoff == 0)
1775 1770 pCmd->Control = 0;
1776 1771 else
1777 1772 pCmd->Control = LE_16(preamble);
1778 1773 pCmd->RadioOn = LE_16(onoff);
1779 1774
1780 1775 retval = mwlExecuteCmd(sc, HostCmd_CMD_802_11_RADIO_CONTROL);
1781 1776 return (retval);
1782 1777 }
1783 1778
1784 1779 static int
1785 1780 mwl_hal_setwmm(struct mwl_softc *sc, int onoff)
1786 1781 {
1787 1782 HostCmd_FW_SetWMMMode *pCmd;
1788 1783 int retval;
1789 1784
1790 1785 _CMD_SETUP(pCmd, HostCmd_FW_SetWMMMode,
1791 1786 HostCmd_CMD_SET_WMM_MODE);
1792 1787 pCmd->Action = LE_16(onoff);
1793 1788
1794 1789 retval = mwlExecuteCmd(sc, HostCmd_CMD_SET_WMM_MODE);
1795 1790 return (retval);
1796 1791 }
1797 1792
1798 1793 /*
1799 1794 * Convert public channel flags definition to a
1800 1795 * value suitable for feeding to the firmware.
1801 1796 * Note this includes byte swapping.
1802 1797 */
1803 1798 static uint32_t
1804 1799 cvtChannelFlags(const MWL_HAL_CHANNEL *chan)
1805 1800 {
1806 1801 uint32_t w;
1807 1802
1808 1803 /*
1809 1804 * NB: f/w only understands FREQ_BAND_5GHZ, supplying the more
1810 1805 * precise band info causes it to lockup (sometimes).
1811 1806 */
1812 1807 w = (chan->channelFlags.FreqBand == MWL_FREQ_BAND_2DOT4GHZ) ?
1813 1808 FREQ_BAND_2DOT4GHZ : FREQ_BAND_5GHZ;
1814 1809 switch (chan->channelFlags.ChnlWidth) {
1815 1810 case MWL_CH_10_MHz_WIDTH:
1816 1811 w |= CH_10_MHz_WIDTH;
1817 1812 break;
1818 1813 case MWL_CH_20_MHz_WIDTH:
1819 1814 w |= CH_20_MHz_WIDTH;
1820 1815 break;
1821 1816 case MWL_CH_40_MHz_WIDTH:
1822 1817 default:
1823 1818 w |= CH_40_MHz_WIDTH;
1824 1819 break;
1825 1820 }
1826 1821 switch (chan->channelFlags.ExtChnlOffset) {
1827 1822 case MWL_EXT_CH_NONE:
1828 1823 w |= EXT_CH_NONE;
1829 1824 break;
1830 1825 case MWL_EXT_CH_ABOVE_CTRL_CH:
1831 1826 w |= EXT_CH_ABOVE_CTRL_CH;
1832 1827 break;
1833 1828 case MWL_EXT_CH_BELOW_CTRL_CH:
1834 1829 w |= EXT_CH_BELOW_CTRL_CH;
1835 1830 break;
1836 1831 }
1837 1832 return (LE_32(w));
1838 1833 }
1839 1834
1840 1835 static int
1841 1836 mwl_hal_setchannel(struct mwl_softc *sc, const MWL_HAL_CHANNEL *chan)
1842 1837 {
1843 1838 HostCmd_FW_SET_RF_CHANNEL *pCmd;
1844 1839 int retval;
1845 1840
1846 1841 _CMD_SETUP(pCmd, HostCmd_FW_SET_RF_CHANNEL, HostCmd_CMD_SET_RF_CHANNEL);
1847 1842 pCmd->Action = LE_16(HostCmd_ACT_GEN_SET);
1848 1843 pCmd->CurrentChannel = chan->channel;
1849 1844 pCmd->ChannelFlags = cvtChannelFlags(chan); /* NB: byte-swapped */
1850 1845
1851 1846 retval = mwlExecuteCmd(sc, HostCmd_CMD_SET_RF_CHANNEL);
1852 1847 return (retval);
1853 1848 }
1854 1849
1855 1850 static int
1856 1851 mwl_hal_settxpower(struct mwl_softc *sc,
1857 1852 const MWL_HAL_CHANNEL *c, uint8_t maxtxpow)
1858 1853 {
1859 1854 HostCmd_DS_802_11_RF_TX_POWER *pCmd;
1860 1855 const struct mwl_hal_channel *hc;
1861 1856 int i = 0, retval;
1862 1857
1863 1858 hc = findhalchannel(sc, c);
1864 1859 if (hc == NULL) {
1865 1860 /* XXX temp while testing */
1866 1861 MWL_DBG(MWL_DBG_HW, "mwl: mwl_hal_settxpower(): "
1867 1862 "no cal data for channel %u band %u width %u ext %u\n",
1868 1863 c->channel, c->channelFlags.FreqBand,
1869 1864 c->channelFlags.ChnlWidth, c->channelFlags.ExtChnlOffset);
1870 1865 return (EINVAL);
1871 1866 }
1872 1867
1873 1868 _CMD_SETUP(pCmd, HostCmd_DS_802_11_RF_TX_POWER,
1874 1869 HostCmd_CMD_802_11_RF_TX_POWER);
1875 1870 pCmd->Action = LE_16(HostCmd_ACT_GEN_SET_LIST);
1876 1871 /* NB: 5Ghz cal data have the channel # in [0]; don't truncate */
1877 1872 if (c->channelFlags.FreqBand == MWL_FREQ_BAND_5GHZ)
1878 1873 pCmd->PowerLevelList[i++] = LE_16(hc->targetPowers[0]);
1879 1874 for (; i < 4; i++) {
1880 1875 uint16_t pow = hc->targetPowers[i];
1881 1876 if (pow > maxtxpow)
1882 1877 pow = maxtxpow;
1883 1878 pCmd->PowerLevelList[i] = LE_16(pow);
1884 1879 }
1885 1880 retval = mwlExecuteCmd(sc, HostCmd_CMD_802_11_RF_TX_POWER);
1886 1881 return (retval);
1887 1882 }
1888 1883
1889 1884 #define RATEVAL(r) ((r) &~ RATE_MCS)
1890 1885 #define RATETYPE(r) (((r) & RATE_MCS) ? HT_RATE_TYPE : LEGACY_RATE_TYPE)
1891 1886
1892 1887 static int
1893 1888 mwl_hal_settxrate(struct mwl_softc *sc, MWL_HAL_TXRATE_HANDLING handling,
1894 1889 const MWL_HAL_TXRATE *rate)
1895 1890 {
1896 1891 HostCmd_FW_USE_FIXED_RATE *pCmd;
1897 1892 FIXED_RATE_ENTRY *fp;
1898 1893 int retval, i, n;
1899 1894
1900 1895 _VCMD_SETUP(pCmd, HostCmd_FW_USE_FIXED_RATE,
1901 1896 HostCmd_CMD_SET_FIXED_RATE);
1902 1897
1903 1898 pCmd->MulticastRate = RATEVAL(rate->McastRate);
1904 1899 pCmd->MultiRateTxType = RATETYPE(rate->McastRate);
1905 1900 /* NB: no rate type field */
1906 1901 pCmd->ManagementRate = RATEVAL(rate->MgtRate);
1907 1902 (void) memset(pCmd->FixedRateTable, 0, sizeof (pCmd->FixedRateTable));
1908 1903 if (handling == RATE_FIXED) {
1909 1904 pCmd->Action = LE_32(HostCmd_ACT_GEN_SET);
1910 1905 pCmd->AllowRateDrop = LE_32(FIXED_RATE_WITHOUT_AUTORATE_DROP);
1911 1906 fp = pCmd->FixedRateTable;
1912 1907 fp->FixedRate =
1913 1908 LE_32(RATEVAL(rate->RateSeries[0].Rate));
1914 1909 fp->FixRateTypeFlags.FixRateType =
1915 1910 LE_32(RATETYPE(rate->RateSeries[0].Rate));
1916 1911 pCmd->EntryCount = LE_32(1);
1917 1912 } else if (handling == RATE_FIXED_DROP) {
1918 1913 pCmd->Action = LE_32(HostCmd_ACT_GEN_SET);
1919 1914 pCmd->AllowRateDrop = LE_32(FIXED_RATE_WITH_AUTO_RATE_DROP);
1920 1915 n = 0;
1921 1916 fp = pCmd->FixedRateTable;
1922 1917 for (i = 0; i < 4; i++) {
1923 1918 if (rate->RateSeries[0].TryCount == 0)
1924 1919 break;
1925 1920 fp->FixRateTypeFlags.FixRateType =
1926 1921 LE_32(RATETYPE(rate->RateSeries[i].Rate));
1927 1922 fp->FixedRate =
1928 1923 LE_32(RATEVAL(rate->RateSeries[i].Rate));
1929 1924 fp->FixRateTypeFlags.RetryCountValid =
1930 1925 LE_32(RETRY_COUNT_VALID);
1931 1926 fp->RetryCount =
1932 1927 LE_32(rate->RateSeries[i].TryCount-1);
1933 1928 n++;
1934 1929 }
1935 1930 pCmd->EntryCount = LE_32(n);
1936 1931 } else
1937 1932 pCmd->Action = LE_32(HostCmd_ACT_NOT_USE_FIXED_RATE);
1938 1933
1939 1934 retval = mwlExecuteCmd(sc, HostCmd_CMD_SET_FIXED_RATE);
1940 1935 return (retval);
1941 1936 }
1942 1937
1943 1938 static int
1944 1939 mwl_hal_settxrate_auto(struct mwl_softc *sc, const MWL_HAL_TXRATE *rate)
1945 1940 {
1946 1941 HostCmd_FW_USE_FIXED_RATE *pCmd;
1947 1942 int retval;
1948 1943
1949 1944 _CMD_SETUP(pCmd, HostCmd_FW_USE_FIXED_RATE,
1950 1945 HostCmd_CMD_SET_FIXED_RATE);
1951 1946
1952 1947 pCmd->MulticastRate = RATEVAL(rate->McastRate);
1953 1948 pCmd->MultiRateTxType = RATETYPE(rate->McastRate);
1954 1949 /* NB: no rate type field */
1955 1950 pCmd->ManagementRate = RATEVAL(rate->MgtRate);
1956 1951 (void) memset(pCmd->FixedRateTable, 0, sizeof (pCmd->FixedRateTable));
1957 1952 pCmd->Action = LE_32(HostCmd_ACT_NOT_USE_FIXED_RATE);
1958 1953
1959 1954 retval = mwlExecuteCmd(sc, HostCmd_CMD_SET_FIXED_RATE);
1960 1955 return (retval);
1961 1956 }
1962 1957
1963 1958 #undef RATEVAL
1964 1959 #undef RATETYPE
1965 1960
1966 1961 /* XXX 0 = indoor, 1 = outdoor */
1967 1962 static int
1968 1963 mwl_hal_setrateadaptmode(struct mwl_softc *sc, uint16_t mode)
1969 1964 {
1970 1965 HostCmd_DS_SET_RATE_ADAPT_MODE *pCmd;
1971 1966 int retval;
1972 1967
1973 1968 _CMD_SETUP(pCmd, HostCmd_DS_SET_RATE_ADAPT_MODE,
1974 1969 HostCmd_CMD_SET_RATE_ADAPT_MODE);
1975 1970 pCmd->Action = LE_16(HostCmd_ACT_GEN_SET);
1976 1971 pCmd->RateAdaptMode = LE_16(mode);
1977 1972
1978 1973 retval = mwlExecuteCmd(sc, HostCmd_CMD_SET_RATE_ADAPT_MODE);
1979 1974 return (retval);
1980 1975 }
1981 1976
1982 1977 static int
1983 1978 mwl_hal_setoptimizationlevel(struct mwl_softc *sc, int level)
1984 1979 {
1985 1980 HostCmd_FW_SET_OPTIMIZATION_LEVEL *pCmd;
1986 1981 int retval;
1987 1982
1988 1983 _CMD_SETUP(pCmd, HostCmd_FW_SET_OPTIMIZATION_LEVEL,
1989 1984 HostCmd_CMD_SET_OPTIMIZATION_LEVEL);
1990 1985 pCmd->OptLevel = (uint8_t)level;
1991 1986
1992 1987 retval = mwlExecuteCmd(sc, HostCmd_CMD_SET_OPTIMIZATION_LEVEL);
1993 1988 return (retval);
1994 1989 }
1995 1990
1996 1991 /*
1997 1992 * Set the region code that selects the radar bin'ing agorithm.
1998 1993 */
1999 1994 static int
2000 1995 mwl_hal_setregioncode(struct mwl_softc *sc, int regionCode)
2001 1996 {
2002 1997 HostCmd_SET_REGIONCODE_INFO *pCmd;
2003 1998 int retval;
2004 1999
2005 2000 _CMD_SETUP(pCmd, HostCmd_SET_REGIONCODE_INFO,
2006 2001 HostCmd_CMD_SET_REGION_CODE);
2007 2002 /* XXX map pseudo-codes to fw codes */
2008 2003 switch (regionCode) {
2009 2004 case DOMAIN_CODE_ETSI_131:
2010 2005 pCmd->regionCode = LE_16(DOMAIN_CODE_ETSI);
2011 2006 break;
2012 2007 default:
2013 2008 pCmd->regionCode = LE_16(regionCode);
2014 2009 break;
2015 2010 }
2016 2011
2017 2012 retval = mwlExecuteCmd(sc, HostCmd_CMD_SET_REGION_CODE);
2018 2013 return (retval);
2019 2014 }
2020 2015
2021 2016 static int
2022 2017 mwl_hal_setassocid(struct mwl_softc *sc,
2023 2018 const uint8_t bssId[IEEE80211_ADDR_LEN], uint16_t assocId)
2024 2019 {
2025 2020 HostCmd_FW_SET_AID *pCmd = (HostCmd_FW_SET_AID *) &sc->sc_cmd_mem[0];
2026 2021 int retval;
2027 2022
2028 2023 _VCMD_SETUP(pCmd, HostCmd_FW_SET_AID, HostCmd_CMD_SET_AID);
2029 2024 pCmd->AssocID = LE_16(assocId);
2030 2025 IEEE80211_ADDR_COPY(&pCmd->MacAddr[0], bssId);
2031 2026
2032 2027 retval = mwlExecuteCmd(sc, HostCmd_CMD_SET_AID);
2033 2028 return (retval);
2034 2029 }
2035 2030
2036 2031 /*
2037 2032 * Inform firmware of tx rate parameters. Called whenever
2038 2033 * user-settable params change and after a channel change.
2039 2034 */
2040 2035 static int
2041 2036 mwl_setrates(struct ieee80211com *ic)
2042 2037 {
2043 2038 struct mwl_softc *sc = (struct mwl_softc *)ic;
2044 2039 MWL_HAL_TXRATE rates;
2045 2040
2046 2041 const struct ieee80211_rateset *rs;
2047 2042 rs = &ic->ic_bss->in_rates;
2048 2043
2049 2044 /*
2050 2045 * Update the h/w rate map.
2051 2046 * NB: 0x80 for MCS is passed through unchanged
2052 2047 */
2053 2048 (void) memset(&rates, 0, sizeof (rates));
2054 2049 /* rate used to send management frames */
2055 2050 rates.MgtRate = rs->ir_rates[0] & IEEE80211_RATE_VAL;
2056 2051 /* rate used to send multicast frames */
2057 2052 rates.McastRate = rates.MgtRate;
2058 2053
2059 2054 return (mwl_hal_settxrate(sc, RATE_AUTO, &rates));
2060 2055 }
2061 2056
2062 2057 /*
2063 2058 * Set packet size threshold for implicit use of RTS.
2064 2059 * Takes effect immediately.
2065 2060 * XXX packet length > threshold =>'s RTS
2066 2061 */
2067 2062 static int
2068 2063 mwl_hal_setrtsthreshold(struct mwl_softc *sc, int threshold)
2069 2064 {
2070 2065 HostCmd_DS_802_11_RTS_THSD *pCmd;
2071 2066 int retval;
2072 2067
2073 2068 _VCMD_SETUP(pCmd, HostCmd_DS_802_11_RTS_THSD,
2074 2069 HostCmd_CMD_802_11_RTS_THSD);
2075 2070 pCmd->Action = LE_16(HostCmd_ACT_GEN_SET);
2076 2071 pCmd->Threshold = LE_16(threshold);
2077 2072
2078 2073 retval = mwlExecuteCmd(sc, HostCmd_CMD_802_11_RTS_THSD);
2079 2074 return (retval);
2080 2075 }
2081 2076
2082 2077 static int
2083 2078 mwl_hal_setcsmode(struct mwl_softc *sc, MWL_HAL_CSMODE csmode)
2084 2079 {
2085 2080 HostCmd_DS_SET_LINKADAPT_CS_MODE *pCmd;
2086 2081 int retval;
2087 2082
2088 2083 _CMD_SETUP(pCmd, HostCmd_DS_SET_LINKADAPT_CS_MODE,
2089 2084 HostCmd_CMD_SET_LINKADAPT_CS_MODE);
2090 2085 pCmd->Action = LE_16(HostCmd_ACT_GEN_SET);
2091 2086 pCmd->CSMode = LE_16(csmode);
2092 2087
2093 2088 retval = mwlExecuteCmd(sc, HostCmd_CMD_SET_LINKADAPT_CS_MODE);
2094 2089 return (retval);
2095 2090 }
2096 2091
2097 2092 static int
2098 2093 mwl_hal_setpromisc(struct mwl_softc *sc, int ena)
2099 2094 {
2100 2095 uint32_t v;
2101 2096
2102 2097 v = mwl_ctl_read4(sc, MACREG_REG_PROMISCUOUS);
2103 2098 mwl_ctl_write4(sc, MACREG_REG_PROMISCUOUS, ena ? v | 1 : v & ~1);
2104 2099
2105 2100 return (0);
2106 2101 }
2107 2102
2108 2103 static int
2109 2104 mwl_hal_start(struct mwl_softc *sc)
2110 2105 {
2111 2106 HostCmd_DS_BSS_START *pCmd;
2112 2107 int retval;
2113 2108
2114 2109 _VCMD_SETUP(pCmd, HostCmd_DS_BSS_START, HostCmd_CMD_BSS_START);
2115 2110 pCmd->Enable = LE_32(HostCmd_ACT_GEN_ON);
2116 2111
2117 2112 retval = mwlExecuteCmd(sc, HostCmd_CMD_BSS_START);
2118 2113 return (retval);
2119 2114 }
2120 2115
2121 2116 /*
2122 2117 * Enable sta-mode operation (disables beacon frame xmit).
2123 2118 */
2124 2119 static int
2125 2120 mwl_hal_setinframode(struct mwl_softc *sc)
2126 2121 {
2127 2122 HostCmd_FW_SET_INFRA_MODE *pCmd;
2128 2123 int retval;
2129 2124
2130 2125 _VCMD_SETUP(pCmd, HostCmd_FW_SET_INFRA_MODE,
2131 2126 HostCmd_CMD_SET_INFRA_MODE);
2132 2127
2133 2128 retval = mwlExecuteCmd(sc, HostCmd_CMD_SET_INFRA_MODE);
2134 2129 return (retval);
2135 2130 }
2136 2131
2137 2132 static int
2138 2133 mwl_hal_stop(struct mwl_softc *sc)
2139 2134 {
2140 2135 HostCmd_DS_BSS_START *pCmd;
2141 2136 int retval;
2142 2137
2143 2138 _VCMD_SETUP(pCmd, HostCmd_DS_BSS_START,
2144 2139 HostCmd_CMD_BSS_START);
2145 2140 pCmd->Enable = LE_32(HostCmd_ACT_GEN_OFF);
2146 2141 retval = mwlExecuteCmd(sc, HostCmd_CMD_BSS_START);
2147 2142
2148 2143 return (retval);
2149 2144 }
2150 2145
2151 2146 static int
2152 2147 mwl_hal_keyset(struct mwl_softc *sc, const MWL_HAL_KEYVAL *kv,
2153 2148 const uint8_t mac[IEEE80211_ADDR_LEN])
2154 2149 {
2155 2150 HostCmd_FW_UPDATE_ENCRYPTION_SET_KEY *pCmd;
2156 2151 int retval;
2157 2152
2158 2153 _VCMD_SETUP(pCmd, HostCmd_FW_UPDATE_ENCRYPTION_SET_KEY,
2159 2154 HostCmd_CMD_UPDATE_ENCRYPTION);
2160 2155 if (kv->keyFlags & (KEY_FLAG_TXGROUPKEY|KEY_FLAG_RXGROUPKEY))
2161 2156 pCmd->ActionType = LE_32(EncrActionTypeSetGroupKey);
2162 2157 else
2163 2158 pCmd->ActionType = LE_32(EncrActionTypeSetKey);
2164 2159 pCmd->KeyParam.Length = LE_16(sizeof (pCmd->KeyParam));
2165 2160 pCmd->KeyParam.KeyTypeId = LE_16(kv->keyTypeId);
2166 2161 pCmd->KeyParam.KeyInfo = LE_32(kv->keyFlags);
2167 2162 pCmd->KeyParam.KeyIndex = LE_32(kv->keyIndex);
2168 2163 /* NB: includes TKIP MIC keys */
2169 2164 (void) memcpy(&pCmd->KeyParam.Key, &kv->key, kv->keyLen);
2170 2165 switch (kv->keyTypeId) {
2171 2166 case KEY_TYPE_ID_WEP:
2172 2167 pCmd->KeyParam.KeyLen = LE_16(kv->keyLen);
2173 2168 break;
2174 2169 case KEY_TYPE_ID_TKIP:
2175 2170 pCmd->KeyParam.KeyLen = LE_16(sizeof (TKIP_TYPE_KEY));
2176 2171 pCmd->KeyParam.Key.TkipKey.TkipRsc.low =
2177 2172 LE_16(kv->key.tkip.rsc.low);
2178 2173 pCmd->KeyParam.Key.TkipKey.TkipRsc.high =
2179 2174 LE_32(kv->key.tkip.rsc.high);
2180 2175 pCmd->KeyParam.Key.TkipKey.TkipTsc.low =
2181 2176 LE_16(kv->key.tkip.tsc.low);
2182 2177 pCmd->KeyParam.Key.TkipKey.TkipTsc.high =
2183 2178 LE_32(kv->key.tkip.tsc.high);
2184 2179 break;
2185 2180 case KEY_TYPE_ID_AES:
2186 2181 pCmd->KeyParam.KeyLen = LE_16(sizeof (AES_TYPE_KEY));
2187 2182 break;
2188 2183 }
2189 2184 #ifdef MWL_MBSS_SUPPORT
2190 2185 IEEE80211_ADDR_COPY(pCmd->KeyParam.Macaddr, mac);
2191 2186 #else
2192 2187 IEEE80211_ADDR_COPY(pCmd->Macaddr, mac);
2193 2188 #endif
2194 2189
2195 2190 retval = mwlExecuteCmd(sc, HostCmd_CMD_UPDATE_ENCRYPTION);
2196 2191 return (retval);
2197 2192 }
2198 2193
2199 2194 static int
2200 2195 mwl_hal_keyreset(struct mwl_softc *sc, const MWL_HAL_KEYVAL *kv,
2201 2196 const uint8_t mac[IEEE80211_ADDR_LEN])
2202 2197 {
2203 2198 HostCmd_FW_UPDATE_ENCRYPTION_SET_KEY *pCmd;
2204 2199 int retval;
2205 2200
2206 2201 _VCMD_SETUP(pCmd, HostCmd_FW_UPDATE_ENCRYPTION_SET_KEY,
2207 2202 HostCmd_CMD_UPDATE_ENCRYPTION);
2208 2203 pCmd->ActionType = LE_16(EncrActionTypeRemoveKey);
2209 2204 pCmd->KeyParam.Length = LE_16(sizeof (pCmd->KeyParam));
2210 2205 pCmd->KeyParam.KeyTypeId = LE_16(kv->keyTypeId);
2211 2206 pCmd->KeyParam.KeyInfo = LE_32(kv->keyFlags);
2212 2207 pCmd->KeyParam.KeyIndex = LE_32(kv->keyIndex);
2213 2208 #ifdef MWL_MBSS_SUPPORT
2214 2209 IEEE80211_ADDR_COPY(pCmd->KeyParam.Macaddr, mac);
2215 2210 #else
2216 2211 IEEE80211_ADDR_COPY(pCmd->Macaddr, mac);
2217 2212 #endif
2218 2213 retval = mwlExecuteCmd(sc, HostCmd_CMD_UPDATE_ENCRYPTION);
|
↓ open down ↓ |
1632 lines elided |
↑ open up ↑ |
2219 2214 return (retval);
2220 2215 }
2221 2216
2222 2217 /* ARGSUSED */
2223 2218 static struct ieee80211_node *
2224 2219 mwl_node_alloc(struct ieee80211com *ic)
2225 2220 {
2226 2221 struct mwl_node *mn;
2227 2222
2228 2223 mn = kmem_zalloc(sizeof (struct mwl_node), KM_SLEEP);
2229 - if (mn == NULL) {
2230 - /* XXX stat+msg */
2231 - MWL_DBG(MWL_DBG_MSG, "mwl: mwl_node_alloc(): "
2232 - "alloc node failed\n");
2233 - return (NULL);
2234 - }
2235 2224 return (&mn->mn_node);
2236 2225 }
2237 2226
2238 2227 static void
2239 2228 mwl_node_free(struct ieee80211_node *ni)
2240 2229 {
2241 2230 struct ieee80211com *ic = ni->in_ic;
2242 2231 struct mwl_node *mn = MWL_NODE(ni);
2243 2232
2244 2233 if (mn->mn_staid != 0) {
2245 2234 // mwl_hal_delstation(mn->mn_hvap, vap->iv_myaddr);
2246 2235 // delstaid(sc, mn->mn_staid);
2247 2236 mn->mn_staid = 0;
2248 2237 }
2249 2238 ic->ic_node_cleanup(ni);
2250 2239 kmem_free(ni, sizeof (struct mwl_node));
2251 2240 }
2252 2241
2253 2242 /*
2254 2243 * Allocate a key cache slot for a unicast key. The
2255 2244 * firmware handles key allocation and every station is
2256 2245 * guaranteed key space so we are always successful.
2257 2246 */
2258 2247 static int
2259 2248 mwl_key_alloc(struct ieee80211com *ic, const struct ieee80211_key *k,
2260 2249 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix)
2261 2250 {
2262 2251 if (k->wk_keyix != IEEE80211_KEYIX_NONE ||
2263 2252 (k->wk_flags & IEEE80211_KEY_GROUP)) {
2264 2253 if (!(&ic->ic_nw_keys[0] <= k &&
2265 2254 k < &ic->ic_nw_keys[IEEE80211_WEP_NKID])) {
2266 2255 /* should not happen */
2267 2256 MWL_DBG(MWL_DBG_CRYPTO, "mwl: mwl_key_alloc(): "
2268 2257 "bogus group key\n");
2269 2258 return (0);
2270 2259 }
2271 2260 /* give the caller what they requested */
2272 2261 *keyix = *rxkeyix = k - ic->ic_nw_keys;
2273 2262 MWL_DBG(MWL_DBG_CRYPTO, "mwl: mwl_key_alloc(): "
2274 2263 "alloc GROUP key keyix %x, rxkeyix %x\n",
2275 2264 *keyix, *rxkeyix);
2276 2265 } else {
2277 2266 /*
2278 2267 * Firmware handles key allocation.
2279 2268 */
2280 2269 *keyix = *rxkeyix = 0;
2281 2270 MWL_DBG(MWL_DBG_CRYPTO, "mwl: mwl_key_alloc(): "
2282 2271 "reset key index in key allocation\n");
2283 2272 }
2284 2273
2285 2274 return (1);
2286 2275 }
2287 2276
2288 2277 /*
2289 2278 * Delete a key entry allocated by mwl_key_alloc.
2290 2279 */
2291 2280 static int
2292 2281 mwl_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k)
2293 2282 {
2294 2283 struct mwl_softc *sc = (struct mwl_softc *)ic;
2295 2284 MWL_HAL_KEYVAL hk;
2296 2285 const uint8_t bcastaddr[IEEE80211_ADDR_LEN] =
2297 2286 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
2298 2287
2299 2288 (void) memset(&hk, 0, sizeof (hk));
2300 2289 hk.keyIndex = k->wk_keyix;
2301 2290 switch (k->wk_cipher->ic_cipher) {
2302 2291 case IEEE80211_CIPHER_WEP:
2303 2292 hk.keyTypeId = KEY_TYPE_ID_WEP;
2304 2293 break;
2305 2294 case IEEE80211_CIPHER_TKIP:
2306 2295 hk.keyTypeId = KEY_TYPE_ID_TKIP;
2307 2296 break;
2308 2297 case IEEE80211_CIPHER_AES_CCM:
2309 2298 hk.keyTypeId = KEY_TYPE_ID_AES;
2310 2299 break;
2311 2300 default:
2312 2301 /* XXX should not happen */
2313 2302 MWL_DBG(MWL_DBG_CRYPTO, "mwl: mwl_key_delete(): "
2314 2303 "unknown cipher %d\n", k->wk_cipher->ic_cipher);
2315 2304 return (0);
2316 2305 }
2317 2306 return (mwl_hal_keyreset(sc, &hk, bcastaddr) == 0);
2318 2307 }
2319 2308
2320 2309 /*
2321 2310 * Set the key cache contents for the specified key. Key cache
2322 2311 * slot(s) must already have been allocated by mwl_key_alloc.
2323 2312 */
2324 2313 /* ARGSUSED */
2325 2314 static int
2326 2315 mwl_key_set(struct ieee80211com *ic, const struct ieee80211_key *k,
2327 2316 const uint8_t mac[IEEE80211_ADDR_LEN])
2328 2317 {
2329 2318 #define GRPXMIT (IEEE80211_KEY_XMIT | IEEE80211_KEY_GROUP)
2330 2319 /* NB: static wep keys are marked GROUP+tx/rx; GTK will be tx or rx */
2331 2320 #define IEEE80211_IS_STATICKEY(k) \
2332 2321 (((k)->wk_flags & (GRPXMIT|IEEE80211_KEY_RECV)) == \
2333 2322 (GRPXMIT|IEEE80211_KEY_RECV))
2334 2323 struct mwl_softc *sc = (struct mwl_softc *)ic;
2335 2324 const struct ieee80211_cipher *cip = k->wk_cipher;
2336 2325 const uint8_t *macaddr;
2337 2326 MWL_HAL_KEYVAL hk;
2338 2327
2339 2328 (void) memset(&hk, 0, sizeof (hk));
2340 2329 hk.keyIndex = k->wk_keyix;
2341 2330 switch (cip->ic_cipher) {
2342 2331 case IEEE80211_CIPHER_WEP:
2343 2332 hk.keyTypeId = KEY_TYPE_ID_WEP;
2344 2333 hk.keyLen = k->wk_keylen;
2345 2334 if (k->wk_keyix == ic->ic_def_txkey)
2346 2335 hk.keyFlags = KEY_FLAG_WEP_TXKEY;
2347 2336 if (!IEEE80211_IS_STATICKEY(k)) {
2348 2337 /* NB: WEP is never used for the PTK */
2349 2338 (void) addgroupflags(&hk, k);
2350 2339 }
2351 2340 break;
2352 2341 case IEEE80211_CIPHER_TKIP:
2353 2342 hk.keyTypeId = KEY_TYPE_ID_TKIP;
2354 2343 hk.key.tkip.tsc.high = (uint32_t)(k->wk_keytsc >> 16);
2355 2344 hk.key.tkip.tsc.low = (uint16_t)k->wk_keytsc;
2356 2345 hk.keyFlags = KEY_FLAG_TSC_VALID | KEY_FLAG_MICKEY_VALID;
2357 2346 hk.keyLen = k->wk_keylen + IEEE80211_MICBUF_SIZE;
2358 2347 if (!addgroupflags(&hk, k))
2359 2348 hk.keyFlags |= KEY_FLAG_PAIRWISE;
2360 2349 break;
2361 2350 case IEEE80211_CIPHER_AES_CCM:
2362 2351 hk.keyTypeId = KEY_TYPE_ID_AES;
2363 2352 hk.keyLen = k->wk_keylen;
2364 2353 if (!addgroupflags(&hk, k))
2365 2354 hk.keyFlags |= KEY_FLAG_PAIRWISE;
2366 2355 break;
2367 2356 default:
2368 2357 /* XXX should not happen */
2369 2358 MWL_DBG(MWL_DBG_CRYPTO, "mwl: mwl_key_set(): "
2370 2359 "unknown cipher %d\n",
2371 2360 k->wk_cipher->ic_cipher);
2372 2361 return (0);
2373 2362 }
2374 2363 /*
2375 2364 * NB: tkip mic keys get copied here too; the layout
2376 2365 * just happens to match that in ieee80211_key.
2377 2366 */
2378 2367 (void) memcpy(hk.key.aes, k->wk_key, hk.keyLen);
2379 2368
2380 2369 /*
2381 2370 * Locate address of sta db entry for writing key;
2382 2371 * the convention unfortunately is somewhat different
2383 2372 * than how net80211, hostapd, and wpa_supplicant think.
2384 2373 */
2385 2374
2386 2375 /*
2387 2376 * NB: keys plumbed before the sta reaches AUTH state
2388 2377 * will be discarded or written to the wrong sta db
2389 2378 * entry because iv_bss is meaningless. This is ok
2390 2379 * (right now) because we handle deferred plumbing of
2391 2380 * WEP keys when the sta reaches AUTH state.
2392 2381 */
2393 2382 macaddr = ic->ic_bss->in_bssid;
2394 2383 if (k->wk_flags & IEEE80211_KEY_XMIT) {
2395 2384 /* XXX plumb to local sta db too for static key wep */
2396 2385 (void) mwl_hal_keyset(sc, &hk, ic->ic_macaddr);
2397 2386 }
2398 2387 return (mwl_hal_keyset(sc, &hk, macaddr) == 0);
2399 2388 #undef IEEE80211_IS_STATICKEY
2400 2389 #undef GRPXMIT
2401 2390 }
2402 2391
2403 2392 /*
2404 2393 * Plumb any static WEP key for the station. This is
2405 2394 * necessary as we must propagate the key from the
2406 2395 * global key table of the vap to each sta db entry.
2407 2396 */
2408 2397 static void
2409 2398 mwl_setanywepkey(struct ieee80211com *ic, const uint8_t mac[IEEE80211_ADDR_LEN])
2410 2399 {
2411 2400 if ((ic->ic_flags & (IEEE80211_F_PRIVACY|IEEE80211_F_WPA)) ==
2412 2401 IEEE80211_F_PRIVACY &&
2413 2402 ic->ic_def_txkey != IEEE80211_KEYIX_NONE &&
2414 2403 ic->ic_nw_keys[ic->ic_def_txkey].wk_keyix != IEEE80211_KEYIX_NONE)
2415 2404 (void) mwl_key_set(ic, &ic->ic_nw_keys[ic->ic_def_txkey], mac);
2416 2405 }
2417 2406
2418 2407 static void
2419 2408 mwl_setglobalkeys(struct ieee80211com *ic)
2420 2409 {
2421 2410 struct ieee80211_key *wk;
2422 2411
2423 2412 wk = &ic->ic_nw_keys[0];
2424 2413 for (; wk < &ic->ic_nw_keys[IEEE80211_WEP_NKID]; wk++)
2425 2414 if (wk->wk_keyix != IEEE80211_KEYIX_NONE)
2426 2415 (void) mwl_key_set(ic, wk, ic->ic_macaddr);
2427 2416 }
2428 2417
2429 2418 static int
2430 2419 addgroupflags(MWL_HAL_KEYVAL *hk, const struct ieee80211_key *k)
2431 2420 {
2432 2421 if (k->wk_flags & IEEE80211_KEY_GROUP) {
2433 2422 if (k->wk_flags & IEEE80211_KEY_XMIT)
2434 2423 hk->keyFlags |= KEY_FLAG_TXGROUPKEY;
2435 2424 if (k->wk_flags & IEEE80211_KEY_RECV)
2436 2425 hk->keyFlags |= KEY_FLAG_RXGROUPKEY;
2437 2426 return (1);
2438 2427 } else
2439 2428 return (0);
2440 2429 }
2441 2430
2442 2431 /*
2443 2432 * Set/change channels.
2444 2433 */
2445 2434 static int
2446 2435 mwl_chan_set(struct mwl_softc *sc, struct mwl_channel *chan)
2447 2436 {
2448 2437 MWL_HAL_CHANNEL hchan;
2449 2438 int maxtxpow;
2450 2439
2451 2440 MWL_DBG(MWL_DBG_HW, "mwl: mwl_chan_set(): "
2452 2441 "chan %u MHz/flags 0x%x\n",
2453 2442 chan->ic_freq, chan->ic_flags);
2454 2443
2455 2444 /*
2456 2445 * Convert to a HAL channel description with
2457 2446 * the flags constrained to reflect the current
2458 2447 * operating mode.
2459 2448 */
2460 2449 mwl_mapchan(&hchan, chan);
2461 2450 mwl_hal_intrset(sc, 0); /* disable interrupts */
2462 2451
2463 2452 (void) mwl_hal_setchannel(sc, &hchan);
2464 2453 /*
2465 2454 * Tx power is cap'd by the regulatory setting and
2466 2455 * possibly a user-set limit. We pass the min of
2467 2456 * these to the hal to apply them to the cal data
2468 2457 * for this channel.
2469 2458 * XXX min bound?
2470 2459 */
2471 2460 maxtxpow = 2 * chan->ic_maxregpower;
2472 2461 if (maxtxpow > 100)
2473 2462 maxtxpow = 100;
2474 2463 (void) mwl_hal_settxpower(sc, &hchan, maxtxpow / 2);
2475 2464 /* NB: potentially change mcast/mgt rates */
2476 2465 (void) mwl_setcurchanrates(sc);
2477 2466
2478 2467 sc->sc_curchan = hchan;
2479 2468 mwl_hal_intrset(sc, sc->sc_imask);
2480 2469
2481 2470 return (0);
2482 2471 }
2483 2472
2484 2473 /*
2485 2474 * Convert net80211 channel to a HAL channel.
2486 2475 */
2487 2476 static void
2488 2477 mwl_mapchan(MWL_HAL_CHANNEL *hc, const struct mwl_channel *chan)
2489 2478 {
2490 2479 hc->channel = chan->ic_ieee;
2491 2480
2492 2481 *(uint32_t *)&hc->channelFlags = 0;
2493 2482 if (((chan)->ic_flags & IEEE80211_CHAN_2GHZ) != 0)
2494 2483 hc->channelFlags.FreqBand = MWL_FREQ_BAND_2DOT4GHZ;
2495 2484 else if (((chan)->ic_flags & IEEE80211_CHAN_5GHZ) != 0)
2496 2485 hc->channelFlags.FreqBand = MWL_FREQ_BAND_5GHZ;
2497 2486 if (((chan)->ic_flags & IEEE80211_CHAN_HT40) != 0) {
2498 2487 hc->channelFlags.ChnlWidth = MWL_CH_40_MHz_WIDTH;
2499 2488 if (((chan)->ic_flags & IEEE80211_CHAN_HT40U) != 0)
2500 2489 hc->channelFlags.ExtChnlOffset =
2501 2490 MWL_EXT_CH_ABOVE_CTRL_CH;
2502 2491 else
2503 2492 hc->channelFlags.ExtChnlOffset =
2504 2493 MWL_EXT_CH_BELOW_CTRL_CH;
2505 2494 } else
2506 2495 hc->channelFlags.ChnlWidth = MWL_CH_20_MHz_WIDTH;
2507 2496 /* XXX 10MHz channels */
2508 2497 }
2509 2498
2510 2499 /*
2511 2500 * Return the phy mode for with the specified channel.
2512 2501 */
2513 2502 enum ieee80211_phymode
2514 2503 mwl_chan2mode(const struct mwl_channel *chan)
2515 2504 {
2516 2505
2517 2506 if (IEEE80211_IS_CHAN_HTA(chan))
2518 2507 return (IEEE80211_MODE_11NA);
2519 2508 else if (IEEE80211_IS_CHAN_HTG(chan))
2520 2509 return (IEEE80211_MODE_11NG);
2521 2510 else if (IEEE80211_IS_CHAN_108G(chan))
2522 2511 return (IEEE80211_MODE_TURBO_G);
2523 2512 else if (IEEE80211_IS_CHAN_ST(chan))
2524 2513 return (IEEE80211_MODE_STURBO_A);
2525 2514 else if (IEEE80211_IS_CHAN_TURBO(chan))
2526 2515 return (IEEE80211_MODE_TURBO_A);
2527 2516 else if (IEEE80211_IS_CHAN_HALF(chan))
2528 2517 return (IEEE80211_MODE_HALF);
2529 2518 else if (IEEE80211_IS_CHAN_QUARTER(chan))
2530 2519 return (IEEE80211_MODE_QUARTER);
2531 2520 else if (IEEE80211_IS_CHAN_A(chan))
2532 2521 return (IEEE80211_MODE_11A);
2533 2522 else if (IEEE80211_IS_CHAN_ANYG(chan))
2534 2523 return (IEEE80211_MODE_11G);
2535 2524 else if (IEEE80211_IS_CHAN_B(chan))
2536 2525 return (IEEE80211_MODE_11B);
2537 2526 else if (IEEE80211_IS_CHAN_FHSS(chan))
2538 2527 return (IEEE80211_MODE_FH);
2539 2528
2540 2529 /* NB: should not get here */
2541 2530 MWL_DBG(MWL_DBG_HW, "mwl: mwl_chan2mode(): "
2542 2531 "cannot map channel to mode; freq %u flags 0x%x\n",
2543 2532 chan->ic_freq, chan->ic_flags);
2544 2533 return (IEEE80211_MODE_11B);
2545 2534 }
2546 2535
2547 2536 /* XXX inline or eliminate? */
2548 2537 const struct ieee80211_rateset *
2549 2538 mwl_get_suprates(struct ieee80211com *ic, const struct mwl_channel *c)
2550 2539 {
2551 2540 /* XXX does this work for 11ng basic rates? */
2552 2541 return (&ic->ic_sup_rates[mwl_chan2mode(c)]);
2553 2542 }
2554 2543
2555 2544 /*
2556 2545 * Inform firmware of tx rate parameters.
2557 2546 * Called after a channel change.
2558 2547 */
2559 2548 static int
2560 2549 mwl_setcurchanrates(struct mwl_softc *sc)
2561 2550 {
2562 2551 struct ieee80211com *ic = &sc->sc_ic;
2563 2552 const struct ieee80211_rateset *rs;
2564 2553 MWL_HAL_TXRATE rates;
2565 2554
2566 2555 (void) memset(&rates, 0, sizeof (rates));
2567 2556 rs = mwl_get_suprates(ic, sc->sc_cur_chan);
2568 2557 /* rate used to send management frames */
2569 2558 rates.MgtRate = rs->ir_rates[0] & IEEE80211_RATE_VAL;
2570 2559 /* rate used to send multicast frames */
2571 2560 rates.McastRate = rates.MgtRate;
2572 2561
2573 2562 return (mwl_hal_settxrate_auto(sc, &rates));
2574 2563 }
2575 2564
2576 2565 static const struct mwl_hal_channel *
2577 2566 findhalchannel(const struct mwl_softc *sc, const MWL_HAL_CHANNEL *c)
2578 2567 {
2579 2568 const struct mwl_hal_channel *hc;
2580 2569 const MWL_HAL_CHANNELINFO *ci;
2581 2570 int chan = c->channel, i;
2582 2571
2583 2572 if (c->channelFlags.FreqBand == MWL_FREQ_BAND_2DOT4GHZ) {
2584 2573 i = chan - 1;
2585 2574 if (c->channelFlags.ChnlWidth == MWL_CH_40_MHz_WIDTH) {
2586 2575 ci = &sc->sc_40M;
2587 2576 if (c->channelFlags.ExtChnlOffset ==
2588 2577 MWL_EXT_CH_BELOW_CTRL_CH)
2589 2578 i -= 4;
2590 2579 } else
2591 2580 ci = &sc->sc_20M;
2592 2581 /* 2.4G channel table is directly indexed */
2593 2582 hc = ((unsigned)i < ci->nchannels) ? &ci->channels[i] : NULL;
2594 2583 } else if (c->channelFlags.FreqBand == MWL_FREQ_BAND_5GHZ) {
2595 2584 if (c->channelFlags.ChnlWidth == MWL_CH_40_MHz_WIDTH) {
2596 2585 ci = &sc->sc_40M_5G;
2597 2586 if (c->channelFlags.ExtChnlOffset ==
2598 2587 MWL_EXT_CH_BELOW_CTRL_CH)
2599 2588 chan -= 4;
2600 2589 } else
2601 2590 ci = &sc->sc_20M_5G;
2602 2591 /* 5GHz channel table is sparse and must be searched */
2603 2592 for (i = 0; i < ci->nchannels; i++)
2604 2593 if (ci->channels[i].ieee == chan)
2605 2594 break;
2606 2595 hc = (i < ci->nchannels) ? &ci->channels[i] : NULL;
2607 2596 } else
2608 2597 hc = NULL;
2609 2598 return (hc);
2610 2599 }
2611 2600
2612 2601 /*
2613 2602 * Map SKU+country code to region code for radar bin'ing.
2614 2603 */
2615 2604 static int
2616 2605 mwl_map2regioncode(const struct mwl_regdomain *rd)
2617 2606 {
2618 2607 switch (rd->regdomain) {
2619 2608 case SKU_FCC:
2620 2609 case SKU_FCC3:
2621 2610 return (DOMAIN_CODE_FCC);
2622 2611 case SKU_CA:
2623 2612 return (DOMAIN_CODE_IC);
2624 2613 case SKU_ETSI:
2625 2614 case SKU_ETSI2:
2626 2615 case SKU_ETSI3:
2627 2616 if (rd->country == CTRY_SPAIN)
2628 2617 return (DOMAIN_CODE_SPAIN);
2629 2618 if (rd->country == CTRY_FRANCE || rd->country == CTRY_FRANCE2)
2630 2619 return (DOMAIN_CODE_FRANCE);
2631 2620 /* XXX force 1.3.1 radar type */
2632 2621 return (DOMAIN_CODE_ETSI_131);
2633 2622 case SKU_JAPAN:
2634 2623 return (DOMAIN_CODE_MKK);
2635 2624 case SKU_ROW:
2636 2625 return (DOMAIN_CODE_DGT); /* Taiwan */
2637 2626 case SKU_APAC:
2638 2627 case SKU_APAC2:
2639 2628 case SKU_APAC3:
2640 2629 return (DOMAIN_CODE_AUS); /* Australia */
2641 2630 }
2642 2631 /* XXX KOREA? */
2643 2632 return (DOMAIN_CODE_FCC); /* XXX? */
2644 2633 }
2645 2634
2646 2635 /*
2647 2636 * Setup the rx data structures. This should only be
2648 2637 * done once or we may get out of sync with the firmware.
2649 2638 */
2650 2639 static int
2651 2640 mwl_startrecv(struct mwl_softc *sc)
2652 2641 {
2653 2642 struct mwl_rx_ring *ring;
2654 2643 struct mwl_rxdesc *ds;
2655 2644 struct mwl_rxbuf *bf, *prev;
2656 2645
2657 2646 int i;
2658 2647
2659 2648 ring = &sc->sc_rxring;
2660 2649 bf = ring->buf;
2661 2650
2662 2651 prev = NULL;
2663 2652 for (i = 0; i < MWL_RX_RING_COUNT; i++, bf++) {
2664 2653 ds = bf->bf_desc;
2665 2654 /*
2666 2655 * NB: DMA buffer contents is known to be unmodified
2667 2656 * so there's no need to flush the data cache.
2668 2657 */
2669 2658
2670 2659 /*
2671 2660 * Setup descriptor.
2672 2661 */
2673 2662 ds->QosCtrl = 0;
2674 2663 ds->RSSI = 0;
2675 2664 ds->Status = EAGLE_RXD_STATUS_IDLE;
2676 2665 ds->Channel = 0;
2677 2666 ds->PktLen = LE_16(MWL_AGGR_SIZE);
2678 2667 ds->SQ2 = 0;
2679 2668 ds->pPhysBuffData = LE_32(bf->bf_baddr);
2680 2669 /* NB: don't touch pPhysNext, set once */
2681 2670 ds->RxControl = EAGLE_RXD_CTRL_DRIVER_OWN;
2682 2671
2683 2672 (void) ddi_dma_sync(ring->rxdesc_dma.dma_hdl,
2684 2673 i * sizeof (struct mwl_rxdesc),
2685 2674 sizeof (struct mwl_rxdesc),
2686 2675 DDI_DMA_SYNC_FORDEV);
2687 2676
2688 2677 if (prev != NULL) {
2689 2678 ds = prev->bf_desc;
2690 2679 ds->pPhysNext = LE_32(bf->bf_daddr);
2691 2680 }
2692 2681 prev = bf;
2693 2682 }
2694 2683
2695 2684 if (prev != NULL) {
2696 2685 ds = prev->bf_desc;
2697 2686 ds->pPhysNext = ring->physaddr;
2698 2687 }
2699 2688
2700 2689 /* set filters, etc. */
2701 2690 (void) mwl_mode_init(sc);
2702 2691
2703 2692 return (0);
2704 2693 }
2705 2694
2706 2695 static int
2707 2696 mwl_mode_init(struct mwl_softc *sc)
2708 2697 {
2709 2698 /*
2710 2699 * NB: Ignore promisc in hostap mode; it's set by the
2711 2700 * bridge. This is wrong but we have no way to
2712 2701 * identify internal requests (from the bridge)
2713 2702 * versus external requests such as for tcpdump.
2714 2703 */
2715 2704 /* mwl_setmcastfilter - not support now */
2716 2705 (void) mwl_hal_setpromisc(sc, 0);
2717 2706
2718 2707 return (0);
2719 2708 }
2720 2709
2721 2710 /*
2722 2711 * Kick the firmware to tell it there are new tx descriptors
2723 2712 * for processing. The driver says what h/w q has work in
2724 2713 * case the f/w ever gets smarter.
2725 2714 */
2726 2715 /* ARGSUSED */
2727 2716 static void
2728 2717 mwl_hal_txstart(struct mwl_softc *sc, int qnum)
2729 2718 {
2730 2719
2731 2720 mwl_ctl_write4(sc, MACREG_REG_H2A_INTERRUPT_EVENTS,
2732 2721 MACREG_H2ARIC_BIT_PPA_READY);
2733 2722 (void) mwl_ctl_read4(sc, MACREG_REG_INT_CODE);
2734 2723 }
2735 2724
2736 2725 static int
2737 2726 mwl_send(ieee80211com_t *ic, mblk_t *mp, uint8_t type)
2738 2727 {
2739 2728 struct mwl_softc *sc = (struct mwl_softc *)ic;
2740 2729 struct mwl_tx_ring *ring;
2741 2730 struct mwl_txdesc *ds;
2742 2731 struct mwl_txbuf *bf;
2743 2732 struct ieee80211_frame *wh, *wh1;
2744 2733 struct ieee80211_node *ni = NULL;
2745 2734
2746 2735 int err, off;
2747 2736 int mblen, pktlen, hdrlen;
2748 2737 mblk_t *m, *m0;
2749 2738 uint8_t *addr_4, *txbuf;
2750 2739 uint16_t *pfwlen;
2751 2740
2752 2741 MWL_TXLOCK(sc);
2753 2742
2754 2743 err = DDI_SUCCESS;
2755 2744 if (!MWL_IS_RUNNING(sc) || MWL_IS_SUSPEND(sc)) {
2756 2745 err = ENXIO;
2757 2746 goto fail1;
2758 2747 }
2759 2748
2760 2749 ring = &sc->sc_txring[1];
2761 2750 if (ring->queued > 15) {
2762 2751 MWL_DBG(MWL_DBG_TX, "mwl: mwl_send(): "
2763 2752 "no txbuf, %d\n", ring->queued);
2764 2753 sc->sc_need_sched = 1;
2765 2754 sc->sc_tx_nobuf++;
2766 2755 err = ENOMEM;
2767 2756 goto fail1;
2768 2757 }
2769 2758
2770 2759 m = allocb(msgdsize(mp) + 32, BPRI_MED);
2771 2760 if (m == NULL) {
2772 2761 MWL_DBG(MWL_DBG_TX, "mwl: mwl_send():"
2773 2762 "can't alloc mblk.\n");
2774 2763 err = DDI_FAILURE;
2775 2764 goto fail1;
2776 2765 }
2777 2766
2778 2767 for (off = 0, m0 = mp; m0 != NULL; m0 = m0->b_cont) {
2779 2768 mblen = MBLKL(m0);
2780 2769 (void) bcopy(m0->b_rptr, m->b_rptr + off, mblen);
2781 2770 off += mblen;
2782 2771 }
2783 2772 m->b_wptr += off;
2784 2773
2785 2774 wh = (struct ieee80211_frame *)m->b_rptr;
2786 2775 ni = ieee80211_find_txnode(ic, wh->i_addr1);
2787 2776 if (ni == NULL) {
2788 2777 err = DDI_FAILURE;
2789 2778 sc->sc_tx_err++;
2790 2779 goto fail2;
2791 2780 }
2792 2781
2793 2782 hdrlen = sizeof (*wh);
2794 2783 pktlen = msgdsize(m);
2795 2784
2796 2785 (void) ieee80211_encap(ic, m, ni);
2797 2786
2798 2787 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
2799 2788 const struct ieee80211_cipher *cip;
2800 2789 struct ieee80211_key *k;
2801 2790 k = ieee80211_crypto_encap(ic, m);
2802 2791 if (k == NULL) {
2803 2792 sc->sc_tx_err++;
2804 2793 err = DDI_FAILURE;
2805 2794 goto fail3;
2806 2795 }
2807 2796
2808 2797 /*
2809 2798 * Adjust the packet length for the crypto additions
2810 2799 * done during encap and any other bits that the f/w
2811 2800 * will add later on.
2812 2801 */
2813 2802 cip = k->wk_cipher;
2814 2803 pktlen += cip->ic_header + cip->ic_miclen + cip->ic_trailer;
2815 2804 /* packet header may have moved, reset our local pointer */
2816 2805 wh = (struct ieee80211_frame *)m->b_rptr;
2817 2806 }
2818 2807
2819 2808 ds = &ring->desc[ring->cur];
2820 2809 bf = &ring->buf[ring->cur];
2821 2810
2822 2811 bf->bf_node = ieee80211_ref_node(ni);
2823 2812 txbuf = (uint8_t *)bf->bf_mem;
2824 2813
2825 2814 /*
2826 2815 * inject FW specific fields into the 802.11 frame
2827 2816 *
2828 2817 * 2 bytes FW len (inject)
2829 2818 * 24 bytes 802.11 frame header
2830 2819 * 6 bytes addr4 (inject)
2831 2820 * n bytes 802.11 frame body
2832 2821 */
2833 2822 pfwlen = (uint16_t *)txbuf;
2834 2823 *pfwlen = pktlen - hdrlen;
2835 2824 wh1 = (struct ieee80211_frame *)(txbuf + 2);
2836 2825 bcopy(wh, wh1, sizeof (struct ieee80211_frame));
2837 2826 addr_4 = txbuf + (sizeof (struct ieee80211_frame) + sizeof (uint16_t));
2838 2827 (void) memset(addr_4, 0, 6);
2839 2828 bcopy(m->b_rptr + sizeof (struct ieee80211_frame), txbuf + 32, *pfwlen);
2840 2829 pktlen += 8;
2841 2830
2842 2831 (void) ddi_dma_sync(bf->txbuf_dma.dma_hdl,
2843 2832 0,
2844 2833 pktlen,
2845 2834 DDI_DMA_SYNC_FORDEV);
2846 2835
2847 2836 ds->QosCtrl = 0;
2848 2837 ds->PktLen = (uint16_t)pktlen;
2849 2838 ds->PktPtr = bf->bf_baddr;
2850 2839 ds->Status = LE_32(EAGLE_TXD_STATUS_FW_OWNED);
2851 2840 ds->Format = 0;
2852 2841 ds->pad = 0;
2853 2842 ds->ack_wcb_addr = 0;
2854 2843 ds->TxPriority = 1;
2855 2844
2856 2845 MWL_DBG(MWL_DBG_TX, "mwl: mwl_send(): "
2857 2846 "tx desc Status %x, DataRate %x, TxPriority %x, QosCtrl %x, "
2858 2847 "PktLen %x, SapPktInfo %x, Format %x, Pad %x, ack_wcb_addr %x\n",
2859 2848 ds->Status, ds->DataRate, ds->TxPriority, ds->QosCtrl, ds->PktLen,
2860 2849 ds->SapPktInfo, ds->Format, ds->pad, ds->ack_wcb_addr);
2861 2850
2862 2851 (void) ddi_dma_sync(ring->txdesc_dma.dma_hdl,
2863 2852 ring->cur * sizeof (struct mwl_txdesc),
2864 2853 sizeof (struct mwl_txdesc),
2865 2854 DDI_DMA_SYNC_FORDEV);
2866 2855
2867 2856 MWL_DBG(MWL_DBG_TX, "mwl: mwl_send(): "
2868 2857 "pktlen = %u, slot = %u, queued = %x\n",
2869 2858 mblen, ring->cur, ring->queued);
2870 2859
2871 2860 ring->queued++;
2872 2861 ring->cur = (ring->cur + 1) % MWL_TX_RING_COUNT;
2873 2862
2874 2863 /*
2875 2864 * NB: We don't need to lock against tx done because
2876 2865 * this just prods the firmware to check the transmit
2877 2866 * descriptors. The firmware will also start fetching
2878 2867 * descriptors by itself if it notices new ones are
2879 2868 * present when it goes to deliver a tx done interrupt
2880 2869 * to the host. So if we race with tx done processing
2881 2870 * it's ok. Delivering the kick here rather than in
2882 2871 * mwl_tx_start is an optimization to avoid poking the
2883 2872 * firmware for each packet.
2884 2873 *
2885 2874 * NB: the queue id isn't used so 0 is ok.
2886 2875 */
2887 2876 mwl_hal_txstart(sc, 0);
2888 2877
2889 2878 ic->ic_stats.is_tx_frags++;
2890 2879 ic->ic_stats.is_tx_bytes += pktlen;
2891 2880
2892 2881 fail3:
2893 2882 ieee80211_free_node(ni);
2894 2883 fail2:
2895 2884 freemsg(m);
2896 2885 fail1:
2897 2886 if ((type & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_DATA ||
2898 2887 err == DDI_SUCCESS)
2899 2888 freemsg(mp);
2900 2889 MWL_TXUNLOCK(sc);
2901 2890 return (err);
2902 2891 }
2903 2892
2904 2893 /*
2905 2894 * This function is called periodically (every 200ms) during scanning to
2906 2895 * switch from one channel to another.
2907 2896 */
2908 2897 static void
2909 2898 mwl_next_scan(void *arg)
2910 2899 {
2911 2900 struct mwl_softc *sc = (struct mwl_softc *)arg;
2912 2901 struct ieee80211com *ic = &sc->sc_ic;
2913 2902
2914 2903 if (ic->ic_state == IEEE80211_S_SCAN)
2915 2904 (void) ieee80211_next_scan(ic);
2916 2905
2917 2906 sc->sc_scan_id = 0;
2918 2907 }
2919 2908
2920 2909 /*
2921 2910 * Convert a legacy rate set to a firmware bitmask.
2922 2911 */
2923 2912 static uint32_t
2924 2913 get_rate_bitmap(const struct ieee80211_rateset *rs)
2925 2914 {
2926 2915 uint32_t rates;
2927 2916 int i;
2928 2917
2929 2918 rates = 0;
2930 2919 for (i = 0; i < rs->ir_nrates; i++)
2931 2920 switch (rs->ir_rates[i] & IEEE80211_RATE_VAL) {
2932 2921 case 2: rates |= 0x001; break;
2933 2922 case 4: rates |= 0x002; break;
2934 2923 case 11: rates |= 0x004; break;
2935 2924 case 22: rates |= 0x008; break;
2936 2925 case 44: rates |= 0x010; break;
2937 2926 case 12: rates |= 0x020; break;
2938 2927 case 18: rates |= 0x040; break;
2939 2928 case 24: rates |= 0x080; break;
2940 2929 case 36: rates |= 0x100; break;
2941 2930 case 48: rates |= 0x200; break;
2942 2931 case 72: rates |= 0x400; break;
2943 2932 case 96: rates |= 0x800; break;
2944 2933 case 108: rates |= 0x1000; break;
2945 2934 }
2946 2935 return (rates);
2947 2936 }
2948 2937
2949 2938 /*
2950 2939 * Craft station database entry for station.
2951 2940 * NB: use host byte order here, the hal handles byte swapping.
2952 2941 */
2953 2942 static MWL_HAL_PEERINFO *
2954 2943 mkpeerinfo(MWL_HAL_PEERINFO *pi, const struct ieee80211_node *ni)
2955 2944 {
2956 2945 (void) memset(pi, 0, sizeof (*pi));
2957 2946 pi->LegacyRateBitMap = get_rate_bitmap(&ni->in_rates);
2958 2947 pi->CapInfo = ni->in_capinfo;
2959 2948 return (pi);
2960 2949 }
2961 2950
2962 2951 static int
2963 2952 mwl_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
2964 2953 {
2965 2954 struct mwl_softc *sc = (struct mwl_softc *)ic;
2966 2955 enum ieee80211_state ostate;
2967 2956 struct ieee80211_channel *ic_chan;
2968 2957 struct ieee80211_node *ni = NULL;
2969 2958 MWL_HAL_PEERINFO pi;
2970 2959 uint32_t chan;
2971 2960
2972 2961 if (sc->sc_scan_id != 0) {
2973 2962 (void) untimeout(sc->sc_scan_id);
2974 2963 sc->sc_scan_id = 0;
2975 2964 }
2976 2965
2977 2966 MWL_GLOCK(sc);
2978 2967
2979 2968 ostate = ic->ic_state;
2980 2969 MWL_DBG(MWL_DBG_MSG, "mwl: mwl_newstate(): "
2981 2970 "ostate %x -> nstate %x\n",
2982 2971 ostate, nstate);
2983 2972
2984 2973 switch (nstate) {
2985 2974 case IEEE80211_S_INIT:
2986 2975 break;
2987 2976 case IEEE80211_S_SCAN:
2988 2977 if (ostate != IEEE80211_S_INIT) {
2989 2978 ic_chan = ic->ic_curchan;
2990 2979 chan = ieee80211_chan2ieee(ic, ic_chan);
2991 2980 if (chan != 0 && chan != IEEE80211_CHAN_ANY) {
2992 2981 sc->sc_cur_chan =
2993 2982 &sc->sc_channels[3 * chan - 2];
2994 2983 MWL_DBG(MWL_DBG_MSG, "mwl: mwl_newstate(): "
2995 2984 "chan num is %u, sc chan is %u\n",
2996 2985 chan, sc->sc_cur_chan->ic_ieee);
2997 2986 (void) mwl_chan_set(sc, sc->sc_cur_chan);
2998 2987 }
2999 2988 }
3000 2989 sc->sc_scan_id = timeout(mwl_next_scan, (void *)sc,
3001 2990 drv_usectohz(250000));
3002 2991 break;
3003 2992 case IEEE80211_S_AUTH:
3004 2993 ic_chan = ic->ic_curchan;
3005 2994 chan = ieee80211_chan2ieee(ic, ic_chan);
3006 2995 sc->sc_cur_chan = &sc->sc_channels[3 * chan - 2];
3007 2996 MWL_DBG(MWL_DBG_MSG, "mwl: mwl_newstate(): "
3008 2997 "chan num is %u, sc chan is %u\n",
3009 2998 chan, sc->sc_cur_chan->ic_ieee);
3010 2999 (void) mwl_chan_set(sc, sc->sc_cur_chan);
3011 3000 ni = ic->ic_bss;
3012 3001 (void) mwl_hal_newstation(sc, ic->ic_macaddr, 0, 0, NULL, 0, 0);
3013 3002 mwl_setanywepkey(ic, ni->in_macaddr);
3014 3003 break;
3015 3004 case IEEE80211_S_ASSOC:
3016 3005 break;
3017 3006 case IEEE80211_S_RUN:
3018 3007 ni = ic->ic_bss;
3019 3008 (void) mwl_hal_newstation(sc,
3020 3009 ic->ic_macaddr, 0, 0, mkpeerinfo(&pi, ni), 0, 0);
3021 3010 mwl_setglobalkeys(ic);
3022 3011 (void) mwl_hal_setassocid(sc,
3023 3012 ic->ic_bss->in_bssid, ic->ic_bss->in_associd);
3024 3013 (void) mwl_setrates(ic);
3025 3014 (void) mwl_hal_setrtsthreshold(sc, ic->ic_rtsthreshold);
3026 3015 (void) mwl_hal_setcsmode(sc, CSMODE_AUTO_ENA);
3027 3016 break;
3028 3017 default:
3029 3018 break;
3030 3019 }
3031 3020
3032 3021 MWL_GUNLOCK(sc);
3033 3022
3034 3023 return (sc->sc_newstate(ic, nstate, arg));
3035 3024 }
3036 3025
3037 3026 /*
3038 3027 * Set the interrupt mask.
3039 3028 */
3040 3029 static void
3041 3030 mwl_hal_intrset(struct mwl_softc *sc, uint32_t mask)
3042 3031 {
3043 3032 mwl_ctl_write4(sc, MACREG_REG_A2H_INTERRUPT_MASK, 0);
3044 3033 (void) mwl_ctl_read4(sc, MACREG_REG_INT_CODE);
3045 3034
3046 3035 sc->sc_hal_imask = mask;
3047 3036 mwl_ctl_write4(sc, MACREG_REG_A2H_INTERRUPT_MASK, mask);
3048 3037 (void) mwl_ctl_read4(sc, MACREG_REG_INT_CODE);
3049 3038 }
3050 3039
3051 3040 /*
3052 3041 * Return the current ISR setting and clear the cause.
3053 3042 */
3054 3043 static void
3055 3044 mwl_hal_getisr(struct mwl_softc *sc, uint32_t *status)
3056 3045 {
3057 3046 uint32_t cause;
3058 3047
3059 3048 cause = mwl_ctl_read4(sc, MACREG_REG_A2H_INTERRUPT_CAUSE);
3060 3049 if (cause == 0xffffffff) { /* card removed */
3061 3050 cause = 0;
3062 3051 } else if (cause != 0) {
3063 3052 /* clear cause bits */
3064 3053 mwl_ctl_write4(sc, MACREG_REG_A2H_INTERRUPT_CAUSE,
3065 3054 cause & ~sc->sc_hal_imask);
3066 3055 (void) mwl_ctl_read4(sc, MACREG_REG_INT_CODE);
3067 3056 cause &= sc->sc_hal_imask;
3068 3057 }
3069 3058 *status = cause;
3070 3059 }
3071 3060
3072 3061 static void
3073 3062 mwl_tx_intr(struct mwl_softc *sc)
3074 3063 {
3075 3064 struct ieee80211com *ic = &sc->sc_ic;
3076 3065 struct mwl_tx_ring *ring;
3077 3066 struct mwl_txdesc *ds;
3078 3067
3079 3068 uint32_t status;
3080 3069
3081 3070 MWL_TXLOCK(sc);
3082 3071
3083 3072 ring = &sc->sc_txring[1];
3084 3073
3085 3074 if (!(ring->queued)) {
3086 3075 MWL_TXUNLOCK(sc);
3087 3076 return;
3088 3077 }
3089 3078
3090 3079 (void) ddi_dma_sync(ring->txdesc_dma.dma_hdl,
3091 3080 0,
3092 3081 ring->txdesc_dma.alength,
3093 3082 DDI_DMA_SYNC_FORCPU);
3094 3083
3095 3084 for (;;) {
3096 3085 ds = &ring->desc[ring->next];
3097 3086
3098 3087 status = LE_32(ds->Status);
3099 3088
3100 3089 if (status & LE_32(EAGLE_TXD_STATUS_FW_OWNED)) {
3101 3090 break;
3102 3091 }
3103 3092
3104 3093 if (status == LE_32(EAGLE_TXD_STATUS_IDLE)) {
3105 3094 break;
3106 3095 }
3107 3096
3108 3097 MWL_DBG(MWL_DBG_TX, "mwl: mwl_tx_intr(): "
3109 3098 "recv tx desc status %x, datarate %x, txpriority %x, "
3110 3099 "QosCtrl %x, pktLen %x, SapPktInfo %x, Format %x, "
3111 3100 "pad %x, ack_wcb_addr %x\n",
3112 3101 ds->Status, ds->DataRate, ds->TxPriority,
3113 3102 ds->QosCtrl, ds->PktLen, ds->SapPktInfo,
3114 3103 ds->Format, ds->pad, ds->ack_wcb_addr);
3115 3104
3116 3105 /* descriptor is no longer valid */
3117 3106 ds->Status = LE_32(EAGLE_TXD_STATUS_IDLE);
3118 3107
3119 3108 (void) ddi_dma_sync(ring->txdesc_dma.dma_hdl,
3120 3109 ring->next * sizeof (struct mwl_txdesc),
3121 3110 sizeof (struct mwl_txdesc),
3122 3111 DDI_DMA_SYNC_FORDEV);
3123 3112
3124 3113 ring->queued--;
3125 3114 ring->next = (ring->next + 1) % MWL_TX_RING_COUNT;
3126 3115 MWL_DBG(MWL_DBG_TX, "mwl: mwl_tx_intr(): "
3127 3116 " tx done idx=%u, queued= %d\n",
3128 3117 ring->next, ring->queued);
3129 3118
3130 3119 if (sc->sc_need_sched &&
3131 3120 (ring->queued < MWL_TX_RING_COUNT)) {
3132 3121 sc->sc_need_sched = 0;
3133 3122 mac_tx_update(ic->ic_mach);
3134 3123 }
3135 3124
3136 3125 }
3137 3126
3138 3127 MWL_TXUNLOCK(sc);
3139 3128 }
3140 3129
3141 3130 /*
3142 3131 * Convert hardware signal strength to rssi. The value
3143 3132 * provided by the device has the noise floor added in;
3144 3133 * we need to compensate for this but we don't have that
3145 3134 * so we use a fixed value.
3146 3135 *
3147 3136 * The offset of 8 is good for both 2.4 and 5GHz. The LNA
3148 3137 * offset is already set as part of the initial gain. This
3149 3138 * will give at least +/- 3dB for 2.4GHz and +/- 5dB for 5GHz.
3150 3139 */
3151 3140 static int
3152 3141 cvtrssi(uint8_t ssi)
3153 3142 {
3154 3143 int rssi = (int)ssi + 8;
3155 3144 /* XXX hack guess until we have a real noise floor */
3156 3145 rssi = 2 * (87 - rssi); /* NB: .5 dBm units */
3157 3146 return (rssi < 0 ? 0 : rssi > 127 ? 127 : rssi);
3158 3147 }
3159 3148
3160 3149 static void
3161 3150 mwl_rx_intr(struct mwl_softc *sc)
3162 3151 {
3163 3152 struct ieee80211com *ic = &sc->sc_ic;
3164 3153 struct mwl_rx_ring *ring;
3165 3154 struct ieee80211_node *ni;
3166 3155 struct ieee80211_frame *wh;
3167 3156
3168 3157 struct mwl_rxbuf *bf;
3169 3158 struct mwl_rxdesc *ds;
3170 3159 mblk_t *mp0;
3171 3160
3172 3161 int ntodo, len, rssi;
3173 3162 uint8_t *data, status;
3174 3163
3175 3164 MWL_RXLOCK(sc);
3176 3165
3177 3166 ring = &sc->sc_rxring;
3178 3167 for (ntodo = MWL_RX_RING_COUNT; ntodo > 0; ntodo--) {
3179 3168 bf = &ring->buf[ring->cur];
3180 3169 ds = bf->bf_desc;
3181 3170 data = bf->bf_mem;
3182 3171
3183 3172 (void) ddi_dma_sync(ring->rxdesc_dma.dma_hdl,
3184 3173 ring->cur * sizeof (struct mwl_rxdesc),
3185 3174 sizeof (struct mwl_rxdesc),
3186 3175 DDI_DMA_SYNC_FORCPU);
3187 3176
3188 3177 if (ds->RxControl != EAGLE_RXD_CTRL_DMA_OWN)
3189 3178 break;
3190 3179
3191 3180 status = ds->Status;
3192 3181 if (status & EAGLE_RXD_STATUS_DECRYPT_ERR_MASK) {
3193 3182 MWL_DBG(MWL_DBG_CRYPTO, "mwl: mwl_rx_intr(): "
3194 3183 "rx decrypt error\n");
3195 3184 sc->sc_rx_err++;
3196 3185 }
3197 3186
3198 3187 /*
3199 3188 * Sync the data buffer.
3200 3189 */
3201 3190 len = LE_16(ds->PktLen);
3202 3191
3203 3192 (void) ddi_dma_sync(bf->rxbuf_dma.dma_hdl,
3204 3193 0,
3205 3194 bf->rxbuf_dma.alength,
3206 3195 DDI_DMA_SYNC_FORCPU);
3207 3196
3208 3197 if (len < 32 || len > sc->sc_dmabuf_size) {
3209 3198 MWL_DBG(MWL_DBG_RX, "mwl: mwl_rx_intr(): "
3210 3199 "packet len error %d\n", len);
3211 3200 sc->sc_rx_err++;
3212 3201 goto rxnext;
3213 3202 }
3214 3203
3215 3204 mp0 = allocb(sc->sc_dmabuf_size, BPRI_MED);
3216 3205 if (mp0 == NULL) {
3217 3206 MWL_DBG(MWL_DBG_RX, "mwl: mwl_rx_intr(): "
3218 3207 "alloc mblk error\n");
3219 3208 sc->sc_rx_nobuf++;
3220 3209 goto rxnext;
3221 3210 }
3222 3211 bcopy(data+ 2, mp0->b_wptr, 24);
3223 3212 mp0->b_wptr += 24;
3224 3213 bcopy(data + 32, mp0->b_wptr, len - 32);
3225 3214 mp0->b_wptr += (len - 32);
3226 3215
3227 3216 wh = (struct ieee80211_frame *)mp0->b_rptr;
3228 3217 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) ==
3229 3218 IEEE80211_FC0_TYPE_CTL) {
3230 3219 freemsg(mp0);
3231 3220 goto rxnext;
3232 3221 }
3233 3222
3234 3223 /*
3235 3224 * The f/w strips WEP header but doesn't clear
3236 3225 * the WEP bit; mark the packet with M_WEP so
3237 3226 * net80211 will treat the data as decrypted.
3238 3227 * While here also clear the PWR_MGT bit since
3239 3228 * power save is handled by the firmware and
3240 3229 * passing this up will potentially cause the
3241 3230 * upper layer to put a station in power save
3242 3231 * (except when configured with MWL_HOST_PS_SUPPORT).
3243 3232 */
3244 3233 #ifdef MWL_HOST_PS_SUPPORT
3245 3234 wh->i_fc[1] &= ~IEEE80211_FC1_WEP;
3246 3235 #else
3247 3236 wh->i_fc[1] &= ~(IEEE80211_FC1_WEP | IEEE80211_FC1_PWR_MGT);
3248 3237 #endif
3249 3238
3250 3239 /* calculate rssi early so we can re-use for each aggregate */
3251 3240 rssi = cvtrssi(ds->RSSI);
3252 3241
3253 3242 ni = ieee80211_find_rxnode(ic, wh);
3254 3243
3255 3244 /* send the frame to the 802.11 layer */
3256 3245 (void) ieee80211_input(ic, mp0, ni, rssi, 0);
3257 3246 ieee80211_free_node(ni);
3258 3247 rxnext:
3259 3248 /*
3260 3249 * Setup descriptor.
3261 3250 */
3262 3251 ds->QosCtrl = 0;
3263 3252 ds->RSSI = 0;
3264 3253 ds->Status = EAGLE_RXD_STATUS_IDLE;
3265 3254 ds->Channel = 0;
3266 3255 ds->PktLen = LE_16(MWL_AGGR_SIZE);
3267 3256 ds->SQ2 = 0;
3268 3257 ds->pPhysBuffData = bf->bf_baddr;
3269 3258 /* NB: don't touch pPhysNext, set once */
3270 3259 ds->RxControl = EAGLE_RXD_CTRL_DRIVER_OWN;
3271 3260
3272 3261 (void) ddi_dma_sync(ring->rxdesc_dma.dma_hdl,
3273 3262 ring->cur * sizeof (struct mwl_rxdesc),
3274 3263 sizeof (struct mwl_rxdesc),
3275 3264 DDI_DMA_SYNC_FORDEV);
3276 3265
3277 3266 /* NB: ignore ENOMEM so we process more descriptors */
3278 3267 ring->cur = (ring->cur + 1) % MWL_RX_RING_COUNT;
3279 3268 }
3280 3269
3281 3270 MWL_RXUNLOCK(sc);
3282 3271 }
3283 3272
3284 3273 /*ARGSUSED*/
3285 3274 static uint_t
3286 3275 mwl_softintr(caddr_t data, caddr_t unused)
3287 3276 {
3288 3277 struct mwl_softc *sc = (struct mwl_softc *)data;
3289 3278
3290 3279 /*
3291 3280 * Check if the soft interrupt is triggered by another
3292 3281 * driver at the same level.
3293 3282 */
3294 3283 MWL_GLOCK(sc);
3295 3284 if (sc->sc_rx_pend) {
3296 3285 sc->sc_rx_pend = 0;
3297 3286 MWL_GUNLOCK(sc);
3298 3287 mwl_rx_intr(sc);
3299 3288 return (DDI_INTR_CLAIMED);
3300 3289 }
3301 3290 MWL_GUNLOCK(sc);
3302 3291
3303 3292 return (DDI_INTR_UNCLAIMED);
3304 3293 }
3305 3294
3306 3295 /*ARGSUSED*/
3307 3296 static uint_t
3308 3297 mwl_intr(caddr_t arg, caddr_t unused)
3309 3298 {
3310 3299 struct mwl_softc *sc = (struct mwl_softc *)arg;
3311 3300 uint32_t status;
3312 3301
3313 3302 MWL_GLOCK(sc);
3314 3303
3315 3304 if (!MWL_IS_RUNNING(sc) || MWL_IS_SUSPEND(sc)) {
3316 3305 MWL_GUNLOCK(sc);
3317 3306 return (DDI_INTR_UNCLAIMED);
3318 3307 }
3319 3308
3320 3309 /*
3321 3310 * Figure out the reason(s) for the interrupt.
3322 3311 */
3323 3312 mwl_hal_getisr(sc, &status); /* NB: clears ISR too */
3324 3313 if (status == 0) {
3325 3314 MWL_GUNLOCK(sc);
3326 3315 return (DDI_INTR_UNCLAIMED);
3327 3316 }
3328 3317
3329 3318 if (status & MACREG_A2HRIC_BIT_RX_RDY) {
3330 3319 sc->sc_rx_pend = 1;
3331 3320 (void) ddi_intr_trigger_softint(sc->sc_softintr_hdl, NULL);
3332 3321 }
3333 3322 if (status & MACREG_A2HRIC_BIT_TX_DONE) {
3334 3323 mwl_tx_intr(sc);
3335 3324 }
3336 3325 if (status & MACREG_A2HRIC_BIT_BA_WATCHDOG) {
3337 3326 MWL_DBG(MWL_DBG_INTR, "mwl: mwl_intr(): "
3338 3327 "ba watchdog\n");
3339 3328 }
3340 3329 if (status & MACREG_A2HRIC_BIT_OPC_DONE) {
3341 3330 MWL_DBG(MWL_DBG_INTR, "mwl: mwl_intr(): "
3342 3331 "opc done\n");
3343 3332 }
3344 3333 if (status & MACREG_A2HRIC_BIT_MAC_EVENT) {
3345 3334 MWL_DBG(MWL_DBG_INTR, "mwl: mwl_intr(): "
3346 3335 "mac event\n");
3347 3336 }
3348 3337 if (status & MACREG_A2HRIC_BIT_ICV_ERROR) {
3349 3338 MWL_DBG(MWL_DBG_INTR, "mwl: mwl_intr(): "
3350 3339 "ICV error\n");
3351 3340 }
3352 3341 if (status & MACREG_A2HRIC_BIT_QUEUE_EMPTY) {
3353 3342 MWL_DBG(MWL_DBG_INTR, "mwl: mwl_intr(): "
3354 3343 "queue empty\n");
3355 3344 }
3356 3345 if (status & MACREG_A2HRIC_BIT_QUEUE_FULL) {
3357 3346 MWL_DBG(MWL_DBG_INTR, "mwl: mwl_intr(): "
3358 3347 "queue full\n");
3359 3348 }
3360 3349 if (status & MACREG_A2HRIC_BIT_RADAR_DETECT) {
3361 3350 MWL_DBG(MWL_DBG_INTR, "mwl: mwl_intr(): "
3362 3351 "radar detect\n");
3363 3352 }
3364 3353 if (status & MACREG_A2HRIC_BIT_CHAN_SWITCH) {
3365 3354 MWL_DBG(MWL_DBG_INTR, "mwl: mwl_intr(): "
3366 3355 "chan switch\n");
3367 3356 }
3368 3357
3369 3358 MWL_GUNLOCK(sc);
3370 3359
3371 3360 return (DDI_INTR_CLAIMED);
3372 3361 }
3373 3362
3374 3363 static int
3375 3364 mwl_init(struct mwl_softc *sc)
3376 3365 {
3377 3366 struct ieee80211com *ic = &sc->sc_ic;
3378 3367 int err = 0;
3379 3368
3380 3369 mwl_hal_intrset(sc, 0);
3381 3370
3382 3371 sc->sc_txantenna = 0; /* h/w default */
3383 3372 sc->sc_rxantenna = 0; /* h/w default */
3384 3373
3385 3374 err = mwl_hal_setantenna(sc, WL_ANTENNATYPE_RX, sc->sc_rxantenna);
3386 3375 if (err != 0) {
3387 3376 MWL_DBG(MWL_DBG_HW, "mwl: mwl_init(): "
3388 3377 "could not set rx antenna\n");
3389 3378 goto fail;
3390 3379 }
3391 3380
3392 3381 err = mwl_hal_setantenna(sc, WL_ANTENNATYPE_TX, sc->sc_txantenna);
3393 3382 if (err != 0) {
3394 3383 MWL_DBG(MWL_DBG_HW, "mwl: init(): "
3395 3384 "could not set tx antenna\n");
3396 3385 goto fail;
3397 3386 }
3398 3387
3399 3388 err = mwl_hal_setradio(sc, 1, WL_AUTO_PREAMBLE);
3400 3389 if (err != 0) {
3401 3390 MWL_DBG(MWL_DBG_HW, "mwl: init(): "
3402 3391 "could not set radio\n");
3403 3392 goto fail;
3404 3393 }
3405 3394
3406 3395 err = mwl_hal_setwmm(sc, (ic->ic_flags & IEEE80211_F_WME) != 0);
3407 3396 if (err != 0) {
3408 3397 MWL_DBG(MWL_DBG_HW, "mwl: init(): "
3409 3398 "could not set wme\n");
3410 3399 goto fail;
3411 3400 }
3412 3401
3413 3402 /* select default channel */
3414 3403 ic->ic_ibss_chan = &ic->ic_sup_channels[0];
3415 3404 ic->ic_curchan = ic->ic_ibss_chan;
3416 3405 sc->sc_cur_chan = &sc->sc_channels[1];
3417 3406
3418 3407 err = mwl_chan_set(sc, sc->sc_cur_chan);
3419 3408 if (err != 0) {
3420 3409 MWL_DBG(MWL_DBG_HW, "mwl: init(): "
3421 3410 "could not set wme\n");
3422 3411 goto fail;
3423 3412 }
3424 3413
3425 3414 err = mwl_hal_setrateadaptmode(sc, 0);
3426 3415 if (err != 0) {
3427 3416 MWL_DBG(MWL_DBG_HW, "mwl: init(): "
3428 3417 "could not set rate adapt mode\n");
3429 3418 goto fail;
3430 3419 }
3431 3420
3432 3421 err = mwl_hal_setoptimizationlevel(sc,
3433 3422 (ic->ic_flags & IEEE80211_F_BURST) != 0);
3434 3423 if (err != 0) {
3435 3424 MWL_DBG(MWL_DBG_HW, "mwl: init(): "
3436 3425 "could not set optimization level\n");
3437 3426 goto fail;
3438 3427 }
3439 3428
3440 3429 err = mwl_hal_setregioncode(sc, mwl_map2regioncode(&sc->sc_regdomain));
3441 3430 if (err != 0) {
3442 3431 MWL_DBG(MWL_DBG_HW, "mwl: init(): "
3443 3432 "could not set regioncode\n");
3444 3433 goto fail;
3445 3434 }
3446 3435
3447 3436 err = mwl_startrecv(sc);
3448 3437 if (err != 0) {
3449 3438 MWL_DBG(MWL_DBG_HW, "mwl: init(): "
3450 3439 "could not set start recv logic\n");
3451 3440 goto fail;
3452 3441 }
3453 3442
3454 3443 /*
3455 3444 * Enable interrupts.
3456 3445 */
3457 3446 sc->sc_imask = MACREG_A2HRIC_BIT_RX_RDY
3458 3447 | MACREG_A2HRIC_BIT_TX_DONE
3459 3448 | MACREG_A2HRIC_BIT_OPC_DONE
3460 3449 | MACREG_A2HRIC_BIT_ICV_ERROR
3461 3450 | MACREG_A2HRIC_BIT_RADAR_DETECT
3462 3451 | MACREG_A2HRIC_BIT_CHAN_SWITCH
3463 3452 | MACREG_A2HRIC_BIT_BA_WATCHDOG
3464 3453 | MACREQ_A2HRIC_BIT_TX_ACK;
3465 3454
3466 3455 mwl_hal_intrset(sc, sc->sc_imask);
3467 3456
3468 3457 err = mwl_hal_start(sc);
3469 3458 if (err != 0) {
3470 3459 MWL_DBG(MWL_DBG_HW, "mwl: init(): "
3471 3460 "could not get hal start\n");
3472 3461 goto fail;
3473 3462 }
3474 3463
3475 3464 err = mwl_hal_setinframode(sc);
3476 3465 if (err != 0) {
3477 3466 MWL_DBG(MWL_DBG_HW, "mwl: init(): "
3478 3467 "could not set infra mode\n");
3479 3468 goto fail;
3480 3469 }
3481 3470
3482 3471 fail:
3483 3472 return (err);
3484 3473 }
3485 3474
3486 3475 static int
3487 3476 mwl_resume(struct mwl_softc *sc)
3488 3477 {
3489 3478 int qid, err = 0;
3490 3479
3491 3480 err = mwl_fwload(sc, NULL);
3492 3481 if (err != 0) {
3493 3482 MWL_DBG(MWL_DBG_SR, "mwl: mwl_resume(): "
3494 3483 "failed to load fw\n");
3495 3484 goto fail;
3496 3485 }
3497 3486
3498 3487 err = mwl_gethwspecs(sc);
3499 3488 if (err != 0) {
3500 3489 MWL_DBG(MWL_DBG_SR, "mwl: mwl_resume(): "
3501 3490 "failed to get hw spec\n");
3502 3491 goto fail;
3503 3492 }
3504 3493
3505 3494 err = mwl_alloc_rx_ring(sc, MWL_RX_RING_COUNT);
3506 3495 if (err != 0) {
3507 3496 MWL_DBG(MWL_DBG_SR, "mwl: mwl_resume(): "
3508 3497 "could not alloc cmd dma buffer\n");
3509 3498 goto fail;
3510 3499 }
3511 3500
3512 3501 for (qid = 0; qid < MWL_NUM_TX_QUEUES; qid++) {
3513 3502 err = mwl_alloc_tx_ring(sc,
3514 3503 &sc->sc_txring[qid], MWL_TX_RING_COUNT);
3515 3504 if (err != 0) {
3516 3505 MWL_DBG(MWL_DBG_SR, "mwl: mwl_resume(): "
3517 3506 "could not alloc tx ring %d\n", qid);
3518 3507 goto fail;
3519 3508 }
3520 3509 }
3521 3510
3522 3511 err = mwl_setupdma(sc);
3523 3512 if (err != 0) {
3524 3513 MWL_DBG(MWL_DBG_SR, "mwl: mwl_resume(): "
3525 3514 "could not setup dma\n");
3526 3515 goto fail;
3527 3516 }
3528 3517
3529 3518 err = mwl_setup_txq(sc);
3530 3519 if (err != 0) {
3531 3520 MWL_DBG(MWL_DBG_SR, "mwl: mwl_resume(): "
3532 3521 "could not setup txq\n");
3533 3522 goto fail;
3534 3523 }
3535 3524
3536 3525 fail:
3537 3526 return (err);
3538 3527 }
3539 3528
3540 3529 static void
3541 3530 mwl_stop(struct mwl_softc *sc)
3542 3531 {
3543 3532 int err;
3544 3533
3545 3534 /* by pass if it's quiesced */
3546 3535 if (!MWL_IS_QUIESCE(sc))
3547 3536 MWL_GLOCK(sc);
3548 3537
3549 3538 err = mwl_hal_stop(sc);
3550 3539 if (err != 0) {
3551 3540 MWL_DBG(MWL_DBG_HW, "mwl: mwl_stop(): "
3552 3541 "could not stop hw\n");
3553 3542 }
3554 3543
3555 3544 /* by pass if it's quiesced */
3556 3545 if (!MWL_IS_QUIESCE(sc))
3557 3546 MWL_GUNLOCK(sc);
3558 3547 }
3559 3548
3560 3549 static int
3561 3550 mwl_m_stat(void *arg, uint_t stat, uint64_t *val)
3562 3551 {
3563 3552 struct mwl_softc *sc = (struct mwl_softc *)arg;
3564 3553 struct ieee80211com *ic = &sc->sc_ic;
3565 3554 struct ieee80211_node *ni = NULL;
3566 3555 struct ieee80211_rateset *rs = NULL;
3567 3556
3568 3557 MWL_GLOCK(sc);
3569 3558 switch (stat) {
3570 3559 case MAC_STAT_IFSPEED:
3571 3560 ni = ic->ic_bss;
3572 3561 rs = &ni->in_rates;
3573 3562 *val = ((ic->ic_fixed_rate == IEEE80211_FIXED_RATE_NONE) ?
3574 3563 (rs->ir_rates[ni->in_txrate] & IEEE80211_RATE_VAL)
3575 3564 : ic->ic_fixed_rate) / 2 * 1000000;
3576 3565 break;
3577 3566 case MAC_STAT_NOXMTBUF:
3578 3567 *val = sc->sc_tx_nobuf;
3579 3568 break;
3580 3569 case MAC_STAT_NORCVBUF:
3581 3570 *val = sc->sc_rx_nobuf;
3582 3571 break;
3583 3572 case MAC_STAT_IERRORS:
3584 3573 *val = sc->sc_rx_err;
3585 3574 break;
3586 3575 case MAC_STAT_RBYTES:
3587 3576 *val = ic->ic_stats.is_rx_bytes;
3588 3577 break;
3589 3578 case MAC_STAT_IPACKETS:
3590 3579 *val = ic->ic_stats.is_rx_frags;
3591 3580 break;
3592 3581 case MAC_STAT_OBYTES:
3593 3582 *val = ic->ic_stats.is_tx_bytes;
3594 3583 break;
3595 3584 case MAC_STAT_OPACKETS:
3596 3585 *val = ic->ic_stats.is_tx_frags;
3597 3586 break;
3598 3587 case MAC_STAT_OERRORS:
3599 3588 case WIFI_STAT_TX_FAILED:
3600 3589 *val = sc->sc_tx_err;
3601 3590 break;
3602 3591 case WIFI_STAT_TX_RETRANS:
3603 3592 *val = sc->sc_tx_retries;
3604 3593 break;
3605 3594 case WIFI_STAT_FCS_ERRORS:
3606 3595 case WIFI_STAT_WEP_ERRORS:
3607 3596 case WIFI_STAT_TX_FRAGS:
3608 3597 case WIFI_STAT_MCAST_TX:
3609 3598 case WIFI_STAT_RTS_SUCCESS:
3610 3599 case WIFI_STAT_RTS_FAILURE:
3611 3600 case WIFI_STAT_ACK_FAILURE:
3612 3601 case WIFI_STAT_RX_FRAGS:
3613 3602 case WIFI_STAT_MCAST_RX:
3614 3603 case WIFI_STAT_RX_DUPS:
3615 3604 MWL_GUNLOCK(sc);
3616 3605 return (ieee80211_stat(ic, stat, val));
3617 3606 default:
3618 3607 MWL_GUNLOCK(sc);
3619 3608 return (ENOTSUP);
3620 3609 }
3621 3610
3622 3611 MWL_GUNLOCK(sc);
3623 3612 return (0);
3624 3613 }
3625 3614
3626 3615 static int
3627 3616 mwl_m_start(void *arg)
3628 3617 {
3629 3618 struct mwl_softc *sc = (struct mwl_softc *)arg;
3630 3619 struct ieee80211com *ic = &sc->sc_ic;
3631 3620 int err;
3632 3621
3633 3622 err = mwl_init(sc);
3634 3623 if (err != DDI_SUCCESS) {
3635 3624 MWL_DBG(MWL_DBG_HW, "mwl: mwl_m_start():"
3636 3625 "Hardware initialization failed\n");
3637 3626 goto fail1;
3638 3627 }
3639 3628
3640 3629 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
3641 3630
3642 3631 MWL_GLOCK(sc);
3643 3632 sc->sc_flags |= MWL_F_RUNNING;
3644 3633 MWL_GUNLOCK(sc);
3645 3634
3646 3635 return (0);
3647 3636 fail1:
3648 3637 mwl_stop(sc);
3649 3638 return (err);
3650 3639 }
3651 3640
3652 3641 static void
3653 3642 mwl_m_stop(void *arg)
3654 3643 {
3655 3644 struct mwl_softc *sc = (struct mwl_softc *)arg;
3656 3645
3657 3646 mwl_stop(sc);
3658 3647
3659 3648 ieee80211_new_state(&sc->sc_ic, IEEE80211_S_INIT, -1);
3660 3649
3661 3650 MWL_GLOCK(sc);
3662 3651 sc->sc_flags &= ~MWL_F_RUNNING;
3663 3652 MWL_GUNLOCK(sc);
3664 3653 }
3665 3654
3666 3655 /*ARGSUSED*/
3667 3656 static int
3668 3657 mwl_m_promisc(void *arg, boolean_t on)
3669 3658 {
3670 3659 struct mwl_softc *sc = (struct mwl_softc *)arg;
3671 3660 int err;
3672 3661
3673 3662 err = mwl_hal_setpromisc(sc, on);
3674 3663
3675 3664 return (err);
3676 3665 }
3677 3666
3678 3667 /*ARGSUSED*/
3679 3668 static int
3680 3669 mwl_m_multicst(void *arg, boolean_t add, const uint8_t *mca)
3681 3670 {
3682 3671 return (ENOTSUP);
3683 3672 }
3684 3673
3685 3674 /*ARGSUSED*/
3686 3675 static int
3687 3676 mwl_m_unicst(void *arg, const uint8_t *macaddr)
3688 3677 {
3689 3678 return (ENOTSUP);
3690 3679 }
3691 3680
3692 3681 static mblk_t *
3693 3682 mwl_m_tx(void *arg, mblk_t *mp)
3694 3683 {
3695 3684 struct mwl_softc *sc = (struct mwl_softc *)arg;
3696 3685 struct ieee80211com *ic = &sc->sc_ic;
3697 3686 mblk_t *next;
3698 3687
3699 3688 if (MWL_IS_SUSPEND(sc)) {
3700 3689 freemsgchain(mp);
3701 3690 return (NULL);
3702 3691 }
3703 3692
3704 3693 /*
3705 3694 * No data frames go out unless we're associated; this
3706 3695 * should not happen as the 802.11 layer does not enable
3707 3696 * the xmit queue until we enter the RUN state.
3708 3697 */
3709 3698 if (ic->ic_state != IEEE80211_S_RUN) {
3710 3699 MWL_DBG(MWL_DBG_TX, "mwl: mwl_m_tx(): "
3711 3700 "discard, state %u\n", ic->ic_state);
3712 3701 freemsgchain(mp);
3713 3702 return (NULL);
3714 3703 }
3715 3704
3716 3705 while (mp != NULL) {
3717 3706 next = mp->b_next;
3718 3707 mp->b_next = NULL;
3719 3708 if (mwl_send(ic, mp, IEEE80211_FC0_TYPE_DATA) !=
3720 3709 DDI_SUCCESS) {
3721 3710 mp->b_next = next;
3722 3711 break;
3723 3712 }
3724 3713 mp = next;
3725 3714 }
3726 3715 return (mp);
3727 3716 }
3728 3717
3729 3718 static void
3730 3719 mwl_m_ioctl(void* arg, queue_t *wq, mblk_t *mp)
3731 3720 {
3732 3721 struct mwl_softc *sc = (struct mwl_softc *)arg;
3733 3722 struct ieee80211com *ic = &sc->sc_ic;
3734 3723 int err;
3735 3724
3736 3725 err = ieee80211_ioctl(ic, wq, mp);
3737 3726 if (err == ENETRESET) {
3738 3727 if (ic->ic_des_esslen) {
3739 3728 if (MWL_IS_RUNNING(sc)) {
3740 3729 (void) mwl_init(sc);
3741 3730 (void) ieee80211_new_state(ic,
3742 3731 IEEE80211_S_SCAN, -1);
3743 3732 }
3744 3733 }
3745 3734 }
3746 3735 }
3747 3736
3748 3737 /*
3749 3738 * Call back function for get/set proporty
3750 3739 */
3751 3740 static int
3752 3741 mwl_m_getprop(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num,
3753 3742 uint_t wldp_length, void *wldp_buf)
3754 3743 {
3755 3744 struct mwl_softc *sc = (struct mwl_softc *)arg;
3756 3745 int err = 0;
3757 3746
3758 3747 err = ieee80211_getprop(&sc->sc_ic, pr_name, wldp_pr_num,
3759 3748 wldp_length, wldp_buf);
3760 3749
3761 3750 return (err);
3762 3751 }
3763 3752
3764 3753 static void
3765 3754 mwl_m_propinfo(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num,
3766 3755 mac_prop_info_handle_t prh)
3767 3756 {
3768 3757 struct mwl_softc *sc = (struct mwl_softc *)arg;
3769 3758
3770 3759 ieee80211_propinfo(&sc->sc_ic, pr_name, wldp_pr_num, prh);
3771 3760 }
3772 3761
3773 3762 static int
3774 3763 mwl_m_setprop(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num,
3775 3764 uint_t wldp_length, const void *wldp_buf)
3776 3765 {
3777 3766 struct mwl_softc *sc = (struct mwl_softc *)arg;
3778 3767 ieee80211com_t *ic = &sc->sc_ic;
3779 3768 int err;
3780 3769
3781 3770 err = ieee80211_setprop(ic, pr_name, wldp_pr_num, wldp_length,
3782 3771 wldp_buf);
3783 3772 if (err == ENETRESET) {
3784 3773 if (ic->ic_des_esslen) {
3785 3774 if (MWL_IS_RUNNING(sc)) {
3786 3775 (void) mwl_init(sc);
3787 3776 (void) ieee80211_new_state(ic,
3788 3777 IEEE80211_S_SCAN, -1);
3789 3778 }
3790 3779 }
3791 3780 err = 0;
3792 3781 }
3793 3782 return (err);
3794 3783 }
3795 3784
3796 3785 static int
3797 3786 mwl_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd)
3798 3787 {
3799 3788 struct mwl_softc *sc;
3800 3789 struct ieee80211com *ic;
3801 3790 int i, err, qid, instance;
3802 3791 int intr_type, intr_count, intr_actual;
3803 3792 char strbuf[32];
3804 3793 uint8_t csz;
3805 3794 uint16_t vendor_id, device_id, command;
3806 3795
3807 3796 wifi_data_t wd = { 0 };
3808 3797 mac_register_t *macp;
3809 3798
3810 3799 switch (cmd) {
3811 3800 case DDI_ATTACH:
3812 3801 break;
3813 3802 case DDI_RESUME:
3814 3803 sc = ddi_get_soft_state(mwl_soft_state_p,
3815 3804 ddi_get_instance(devinfo));
3816 3805 ASSERT(sc != NULL);
3817 3806 MWL_GLOCK(sc);
3818 3807 sc->sc_flags &= ~MWL_F_SUSPEND;
3819 3808 MWL_GUNLOCK(sc);
3820 3809 if (mwl_resume(sc) != 0) {
3821 3810 MWL_DBG(MWL_DBG_SR, "mwl: mwl_attach(): "
3822 3811 "failed to resume\n");
3823 3812 return (DDI_FAILURE);
3824 3813 }
3825 3814 if (MWL_IS_RUNNING(sc)) {
3826 3815 (void) mwl_init(sc);
3827 3816 ieee80211_new_state(&sc->sc_ic, IEEE80211_S_INIT, -1);
3828 3817 }
3829 3818 MWL_DBG(MWL_DBG_SR, "mwl: mwl_attach(): "
3830 3819 "resume now\n");
3831 3820 return (DDI_SUCCESS);
3832 3821 default:
3833 3822 return (DDI_FAILURE);
3834 3823 }
3835 3824
3836 3825 instance = ddi_get_instance(devinfo);
3837 3826 if (ddi_soft_state_zalloc(mwl_soft_state_p,
3838 3827 ddi_get_instance(devinfo)) != DDI_SUCCESS) {
3839 3828 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
3840 3829 "Unable to alloc soft state\n");
3841 3830 return (DDI_FAILURE);
3842 3831 }
3843 3832
3844 3833 sc = ddi_get_soft_state(mwl_soft_state_p, ddi_get_instance(devinfo));
3845 3834 ic = &sc->sc_ic;
3846 3835 sc->sc_dev = devinfo;
3847 3836
3848 3837 /* PCI configuration space */
3849 3838 err = ddi_regs_map_setup(devinfo, 0, (caddr_t *)&sc->sc_cfg_base, 0, 0,
3850 3839 &mwl_reg_accattr, &sc->sc_cfg_handle);
3851 3840 if (err != DDI_SUCCESS) {
3852 3841 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
3853 3842 "ddi_regs_map_setup() failed");
3854 3843 goto attach_fail0;
3855 3844 }
3856 3845 csz = ddi_get8(sc->sc_cfg_handle,
3857 3846 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_CACHE_LINESZ));
3858 3847 if (!csz)
3859 3848 csz = 16;
3860 3849 sc->sc_cachelsz = csz << 2;
3861 3850 sc->sc_dmabuf_size = roundup(IEEE80211_MAX_LEN, sc->sc_cachelsz);
3862 3851 vendor_id = ddi_get16(sc->sc_cfg_handle,
3863 3852 (uint16_t *)(sc->sc_cfg_base + PCI_CONF_VENID));
3864 3853 device_id = ddi_get16(sc->sc_cfg_handle,
3865 3854 (uint16_t *)(sc->sc_cfg_base + PCI_CONF_DEVID));
3866 3855 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
3867 3856 "vendor 0x%x, device id 0x%x, cache size %d\n",
3868 3857 vendor_id, device_id, csz);
3869 3858
3870 3859 /*
3871 3860 * Enable response to memory space accesses,
3872 3861 * and enabe bus master.
3873 3862 */
3874 3863 command = PCI_COMM_MAE | PCI_COMM_ME;
3875 3864 ddi_put16(sc->sc_cfg_handle,
3876 3865 (uint16_t *)((uintptr_t)(sc->sc_cfg_base) + PCI_CONF_COMM),
3877 3866 command);
3878 3867 ddi_put8(sc->sc_cfg_handle,
3879 3868 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_LATENCY_TIMER), 0xa8);
3880 3869 ddi_put8(sc->sc_cfg_handle,
3881 3870 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_ILINE), 0x10);
3882 3871
3883 3872 /* BAR0 */
3884 3873 err = ddi_regs_map_setup(devinfo, 1,
3885 3874 &sc->sc_mem_base, 0, 0, &mwl_reg_accattr, &sc->sc_mem_handle);
3886 3875 if (err != DDI_SUCCESS) {
3887 3876 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
3888 3877 "i/o space failed");
3889 3878 goto attach_fail1;
3890 3879 }
3891 3880
3892 3881 /* BAR1 */
3893 3882 err = ddi_regs_map_setup(devinfo, 2,
3894 3883 &sc->sc_io_base, 0, 0, &mwl_reg_accattr, &sc->sc_io_handle);
3895 3884 if (err != DDI_SUCCESS) {
3896 3885 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
3897 3886 "memory space failed");
3898 3887 goto attach_fail2;
3899 3888 }
3900 3889
3901 3890 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
3902 3891 "PCI configuration is done successfully\n");
3903 3892
3904 3893 /*
3905 3894 * Alloc cmd DMA buffer for firmware download
3906 3895 */
3907 3896 err = mwl_alloc_cmdbuf(sc);
3908 3897 if (err != 0) {
3909 3898 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
3910 3899 "could not alloc cmd dma buffer\n");
3911 3900 goto attach_fail3;
3912 3901 }
3913 3902
3914 3903 sc->sc_imask = 0;
3915 3904 sc->sc_hw_flags = 0;
3916 3905 sc->sc_flags = 0;
3917 3906
3918 3907 /*
3919 3908 * Some cards have SDRAM. When loading firmware we need
3920 3909 * to reset the SDRAM controller prior to doing this.
3921 3910 * When the SDRAMSIZE is non-zero we do that work in
3922 3911 * mwl_hal_fwload.
3923 3912 */
3924 3913 switch (device_id) {
3925 3914 case 0x2a02: /* CB82 */
3926 3915 case 0x2a03: /* CB85 */
3927 3916 case 0x2a08: /* MC85_B1 */
3928 3917 case 0x2a0b: /* CB85AP */
3929 3918 case 0x2a24:
3930 3919 sc->sc_SDRAMSIZE_Addr = 0x40fe70b7; /* 8M SDRAM */
3931 3920 break;
3932 3921 case 0x2a04: /* MC85 */
3933 3922 sc->sc_SDRAMSIZE_Addr = 0x40fc70b7; /* 16M SDRAM */
3934 3923 break;
3935 3924 default:
3936 3925 break;
3937 3926 }
3938 3927
3939 3928 err = mwl_fwload(sc, NULL);
3940 3929 if (err != 0) {
3941 3930 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
3942 3931 "firmware download failed\n");
3943 3932 goto attach_fail4;
3944 3933 }
3945 3934
3946 3935 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
3947 3936 "firmware download successfully\n");
3948 3937
3949 3938 err = mwl_gethwspecs(sc);
3950 3939 if (err != 0) {
3951 3940 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
3952 3941 "failed to get hw spec\n");
3953 3942 goto attach_fail4;
3954 3943 }
3955 3944
3956 3945 err = mwl_getchannels(sc);
3957 3946 if (err != 0) {
3958 3947 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
3959 3948 "failed to get channels\n");
3960 3949 goto attach_fail4;
3961 3950 }
3962 3951
3963 3952 /*
3964 3953 * Alloc rx DMA buffer
3965 3954 */
3966 3955 err = mwl_alloc_rx_ring(sc, MWL_RX_RING_COUNT);
3967 3956 if (err != 0) {
3968 3957 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
3969 3958 "could not alloc cmd dma buffer\n");
3970 3959 goto attach_fail5;
3971 3960 }
3972 3961
3973 3962 /*
3974 3963 * Alloc rx DMA buffer
3975 3964 */
3976 3965 for (qid = 0; qid < MWL_NUM_TX_QUEUES; qid++) {
3977 3966 err = mwl_alloc_tx_ring(sc,
3978 3967 &sc->sc_txring[qid], MWL_TX_RING_COUNT);
3979 3968 if (err != 0) {
3980 3969 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
3981 3970 "could not alloc tx ring %d\n", qid);
3982 3971 goto attach_fail6;
3983 3972 }
3984 3973 }
3985 3974
3986 3975 err = mwl_setupdma(sc);
3987 3976 if (err != 0) {
3988 3977 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
3989 3978 "could not setup dma\n");
3990 3979 goto attach_fail6;
3991 3980 }
3992 3981
3993 3982 err = mwl_setup_txq(sc);
3994 3983 if (err != 0) {
3995 3984 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
3996 3985 "could not setup txq\n");
3997 3986 goto attach_fail6;
3998 3987 }
3999 3988
4000 3989 IEEE80211_ADDR_COPY(ic->ic_macaddr, sc->sc_hwspecs.macAddr);
4001 3990 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
4002 3991 "mwl MAC:%2x:%2x:%2x:%2x:%2x:%2x\n",
4003 3992 ic->ic_macaddr[0],
4004 3993 ic->ic_macaddr[1],
4005 3994 ic->ic_macaddr[2],
4006 3995 ic->ic_macaddr[3],
4007 3996 ic->ic_macaddr[4],
4008 3997 ic->ic_macaddr[5]);
4009 3998
4010 3999 err = mwl_hal_setmac_locked(sc, ic->ic_macaddr);
4011 4000 if (err != 0) { /* NB: mwl_setupdma prints msg */
4012 4001 MWL_DBG(MWL_DBG_ATTACH, "mwl: attach(): "
4013 4002 "could not set mac\n");
4014 4003 goto attach_fail6;
4015 4004 }
4016 4005
4017 4006 mutex_init(&sc->sc_glock, NULL, MUTEX_DRIVER, NULL);
4018 4007 mutex_init(&sc->sc_rxlock, NULL, MUTEX_DRIVER, NULL);
4019 4008 mutex_init(&sc->sc_txlock, NULL, MUTEX_DRIVER, NULL);
4020 4009
4021 4010
4022 4011 /* set supported rates */
4023 4012 ic->ic_sup_rates[IEEE80211_MODE_11B] = mwl_rateset_11b;
4024 4013 ic->ic_sup_rates[IEEE80211_MODE_11G] = mwl_rateset_11g;
4025 4014
4026 4015 /* set supported .11b and .11g channels (1 through 14) */
4027 4016 for (i = 1; i <= 14; i++) {
4028 4017 ic->ic_sup_channels[i].ich_freq =
4029 4018 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ);
4030 4019 ic->ic_sup_channels[i].ich_flags =
4031 4020 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ;
4032 4021 }
4033 4022
4034 4023 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
4035 4024 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
4036 4025 ic->ic_state = IEEE80211_S_INIT;
4037 4026
4038 4027 /* set device capabilities */
4039 4028 ic->ic_caps =
4040 4029 IEEE80211_C_TXPMGT | /* tx power management */
4041 4030 IEEE80211_C_SHPREAMBLE | /* short preamble supported */
4042 4031 IEEE80211_C_SHSLOT; /* short slot time supported */
4043 4032
4044 4033 /* WPA/WPA2 support */
4045 4034 ic->ic_caps |= IEEE80211_C_WPA; /* Support WPA/WPA2 */
4046 4035
4047 4036 /* Enable hardware encryption */
4048 4037 ic->ic_caps |= IEEE80211_C_WEP | IEEE80211_C_TKIP | IEEE80211_C_AES_CCM;
4049 4038
4050 4039 ic->ic_xmit = mwl_send;
4051 4040
4052 4041 ieee80211_attach(ic);
4053 4042
4054 4043 /* register WPA door */
4055 4044 ieee80211_register_door(ic, ddi_driver_name(devinfo),
4056 4045 ddi_get_instance(devinfo));
4057 4046
4058 4047 /* override state transition machine */
4059 4048 sc->sc_newstate = ic->ic_newstate;
4060 4049 ic->ic_newstate = mwl_newstate;
4061 4050 ic->ic_node_alloc = mwl_node_alloc;
4062 4051 ic->ic_node_free = mwl_node_free;
4063 4052 ic->ic_crypto.cs_max_keyix = 0;
4064 4053 ic->ic_crypto.cs_key_alloc = mwl_key_alloc;
4065 4054 ic->ic_crypto.cs_key_delete = mwl_key_delete;
4066 4055 ic->ic_crypto.cs_key_set = mwl_key_set;
4067 4056
4068 4057 ieee80211_media_init(ic);
4069 4058
4070 4059 ic->ic_def_txkey = 0;
4071 4060
4072 4061 err = mwl_hal_newstation(sc, ic->ic_macaddr, 0, 0, NULL, 0, 0);
4073 4062 if (err != 0) {
4074 4063 MWL_DBG(MWL_DBG_ATTACH, "mwl: attach(): "
4075 4064 "could not create new station\n");
4076 4065 goto attach_fail7;
4077 4066 }
4078 4067
4079 4068 IEEE80211_ADDR_COPY(ic->ic_bss->in_bssid, ic->ic_macaddr);
4080 4069 // mwl_setglobalkeys(ic);
4081 4070
4082 4071 err = ddi_intr_get_supported_types(devinfo, &intr_type);
4083 4072 if ((err != DDI_SUCCESS) || (!(intr_type & DDI_INTR_TYPE_FIXED))) {
4084 4073 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
4085 4074 "fixed type interrupt is not supported\n");
4086 4075 goto attach_fail7;
4087 4076 }
4088 4077
4089 4078 err = ddi_intr_get_nintrs(devinfo, DDI_INTR_TYPE_FIXED, &intr_count);
4090 4079 if ((err != DDI_SUCCESS) || (intr_count != 1)) {
4091 4080 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
4092 4081 "no fixed interrupts\n");
4093 4082 goto attach_fail7;
4094 4083 }
4095 4084
4096 4085 sc->sc_intr_htable = kmem_zalloc(sizeof (ddi_intr_handle_t), KM_SLEEP);
4097 4086
4098 4087 err = ddi_intr_alloc(devinfo, sc->sc_intr_htable,
4099 4088 DDI_INTR_TYPE_FIXED, 0, intr_count, &intr_actual, 0);
4100 4089 if ((err != DDI_SUCCESS) || (intr_actual != 1)) {
4101 4090 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
4102 4091 "ddi_intr_alloc() failed 0x%x\n", err);
4103 4092 goto attach_fail8;
4104 4093 }
4105 4094
4106 4095 err = ddi_intr_get_pri(sc->sc_intr_htable[0], &sc->sc_intr_pri);
4107 4096 if (err != DDI_SUCCESS) {
4108 4097 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
4109 4098 "ddi_intr_get_pri() failed 0x%x\n", err);
4110 4099 goto attach_fail9;
4111 4100 }
4112 4101
4113 4102 err = ddi_intr_add_softint(devinfo, &sc->sc_softintr_hdl,
4114 4103 DDI_INTR_SOFTPRI_MAX, mwl_softintr, (caddr_t)sc);
4115 4104 if (err != DDI_SUCCESS) {
4116 4105 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
4117 4106 "ddi_add_softintr() failed");
4118 4107 goto attach_fail9;
4119 4108 }
4120 4109
4121 4110 err = ddi_intr_add_handler(sc->sc_intr_htable[0], mwl_intr,
4122 4111 (caddr_t)sc, NULL);
4123 4112 if (err != DDI_SUCCESS) {
4124 4113 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
4125 4114 "ddi_intr_addr_handle() failed\n");
4126 4115 goto attach_fail10;
4127 4116 }
4128 4117
4129 4118 err = ddi_intr_enable(sc->sc_intr_htable[0]);
4130 4119 if (err != DDI_SUCCESS) {
4131 4120 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
4132 4121 "ddi_intr_enable() failed\n");
4133 4122 goto attach_fail11;
4134 4123 }
4135 4124
4136 4125 /*
4137 4126 * Provide initial settings for the WiFi plugin; whenever this
4138 4127 * information changes, we need to call mac_plugindata_update()
4139 4128 */
4140 4129 wd.wd_opmode = ic->ic_opmode;
4141 4130 wd.wd_secalloc = WIFI_SEC_NONE;
4142 4131 IEEE80211_ADDR_COPY(wd.wd_bssid, ic->ic_bss->in_bssid);
4143 4132
4144 4133 if ((macp = mac_alloc(MAC_VERSION)) == NULL) {
4145 4134 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
4146 4135 "MAC version mismatch\n");
4147 4136 goto attach_fail12;
4148 4137 }
4149 4138
4150 4139 macp->m_type_ident = MAC_PLUGIN_IDENT_WIFI;
4151 4140 macp->m_driver = sc;
4152 4141 macp->m_dip = devinfo;
4153 4142 macp->m_src_addr = ic->ic_macaddr;
4154 4143 macp->m_callbacks = &mwl_m_callbacks;
4155 4144 macp->m_min_sdu = 0;
4156 4145 macp->m_max_sdu = IEEE80211_MTU;
4157 4146 macp->m_pdata = &wd;
4158 4147 macp->m_pdata_size = sizeof (wd);
4159 4148
4160 4149 err = mac_register(macp, &ic->ic_mach);
4161 4150 mac_free(macp);
4162 4151 if (err != 0) {
4163 4152 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
4164 4153 "mac_register err %x\n", err);
4165 4154 goto attach_fail12;
4166 4155 }
4167 4156
4168 4157 /*
4169 4158 * Create minor node of type DDI_NT_NET_WIFI
4170 4159 */
4171 4160 (void) snprintf(strbuf, sizeof (strbuf), "%s%d",
4172 4161 "mwl", instance);
4173 4162 err = ddi_create_minor_node(devinfo, strbuf, S_IFCHR,
4174 4163 instance + 1, DDI_NT_NET_WIFI, 0);
4175 4164 if (err != 0) {
4176 4165 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
4177 4166 "create minor node error\n");
4178 4167 goto attach_fail13;
4179 4168 }
4180 4169
4181 4170 /*
4182 4171 * Notify link is down now
4183 4172 */
4184 4173 mac_link_update(ic->ic_mach, LINK_STATE_DOWN);
4185 4174
4186 4175 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
4187 4176 "driver attach successfully\n");
4188 4177 return (DDI_SUCCESS);
4189 4178
4190 4179 attach_fail13:
4191 4180 (void) mac_disable(ic->ic_mach);
4192 4181 (void) mac_unregister(ic->ic_mach);
4193 4182 attach_fail12:
4194 4183 (void) ddi_intr_disable(sc->sc_intr_htable[0]);
4195 4184 attach_fail11:
4196 4185 (void) ddi_intr_remove_handler(sc->sc_intr_htable[0]);
4197 4186 attach_fail10:
4198 4187 (void) ddi_intr_remove_softint(sc->sc_softintr_hdl);
4199 4188 sc->sc_softintr_hdl = NULL;
4200 4189 attach_fail9:
4201 4190 (void) ddi_intr_free(sc->sc_intr_htable[0]);
4202 4191 attach_fail8:
4203 4192 kmem_free(sc->sc_intr_htable, sizeof (ddi_intr_handle_t));
4204 4193 attach_fail7:
4205 4194 mutex_destroy(&sc->sc_txlock);
4206 4195 mutex_destroy(&sc->sc_rxlock);
4207 4196 mutex_destroy(&sc->sc_glock);
4208 4197 attach_fail6:
4209 4198 while (--qid >= 0)
4210 4199 mwl_free_tx_ring(sc, &sc->sc_txring[qid]);
4211 4200 attach_fail5:
4212 4201 mwl_free_rx_ring(sc);
4213 4202 attach_fail4:
4214 4203 mwl_free_cmdbuf(sc);
4215 4204 attach_fail3:
4216 4205 ddi_regs_map_free(&sc->sc_mem_handle);
4217 4206 attach_fail2:
4218 4207 ddi_regs_map_free(&sc->sc_io_handle);
4219 4208 attach_fail1:
4220 4209 ddi_regs_map_free(&sc->sc_cfg_handle);
4221 4210 attach_fail0:
4222 4211 ddi_soft_state_free(mwl_soft_state_p, ddi_get_instance(devinfo));
4223 4212 return (DDI_FAILURE);
4224 4213 }
4225 4214
4226 4215 static int32_t
4227 4216 mwl_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd)
4228 4217 {
4229 4218 struct mwl_softc *sc;
4230 4219 int qid;
4231 4220
4232 4221 sc = ddi_get_soft_state(mwl_soft_state_p, ddi_get_instance(devinfo));
4233 4222 ASSERT(sc != NULL);
4234 4223
4235 4224 switch (cmd) {
4236 4225 case DDI_DETACH:
4237 4226 break;
4238 4227 case DDI_SUSPEND:
4239 4228 if (MWL_IS_RUNNING(sc))
4240 4229 mwl_stop(sc);
4241 4230 for (qid = 0; qid < MWL_NUM_TX_QUEUES; qid++)
4242 4231 mwl_free_tx_ring(sc, &sc->sc_txring[qid]);
4243 4232 mwl_free_rx_ring(sc);
4244 4233 MWL_GLOCK(sc);
4245 4234 sc->sc_flags |= MWL_F_SUSPEND;
4246 4235 MWL_GUNLOCK(sc);
4247 4236 MWL_DBG(MWL_DBG_SR, "mwl: mwl_detach(): "
4248 4237 "suspend now\n");
4249 4238 return (DDI_SUCCESS);
4250 4239 default:
4251 4240 return (DDI_FAILURE);
4252 4241 }
4253 4242
4254 4243 if (mac_disable(sc->sc_ic.ic_mach) != 0)
4255 4244 return (DDI_FAILURE);
4256 4245
4257 4246 /*
4258 4247 * Unregister from the MAC layer subsystem
4259 4248 */
4260 4249 (void) mac_unregister(sc->sc_ic.ic_mach);
4261 4250
4262 4251 (void) ddi_intr_remove_softint(sc->sc_softintr_hdl);
4263 4252 sc->sc_softintr_hdl = NULL;
4264 4253 (void) ddi_intr_disable(sc->sc_intr_htable[0]);
4265 4254 (void) ddi_intr_remove_handler(sc->sc_intr_htable[0]);
4266 4255 (void) ddi_intr_free(sc->sc_intr_htable[0]);
4267 4256 kmem_free(sc->sc_intr_htable, sizeof (ddi_intr_handle_t));
4268 4257
4269 4258 /*
4270 4259 * detach ieee80211 layer
4271 4260 */
4272 4261 ieee80211_detach(&sc->sc_ic);
4273 4262
4274 4263
4275 4264 for (qid = 0; qid < MWL_NUM_TX_QUEUES; qid++)
4276 4265 mwl_free_tx_ring(sc, &sc->sc_txring[qid]);
4277 4266 mwl_free_rx_ring(sc);
4278 4267 mwl_free_cmdbuf(sc);
4279 4268
4280 4269 mutex_destroy(&sc->sc_txlock);
4281 4270 mutex_destroy(&sc->sc_rxlock);
4282 4271 mutex_destroy(&sc->sc_glock);
4283 4272
4284 4273 ddi_regs_map_free(&sc->sc_mem_handle);
4285 4274 ddi_regs_map_free(&sc->sc_io_handle);
4286 4275 ddi_regs_map_free(&sc->sc_cfg_handle);
4287 4276
4288 4277 ddi_remove_minor_node(devinfo, NULL);
4289 4278 ddi_soft_state_free(mwl_soft_state_p, ddi_get_instance(devinfo));
4290 4279
4291 4280 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_detach(): "
4292 4281 "detach successfully\n");
4293 4282 return (DDI_SUCCESS);
4294 4283 }
4295 4284
4296 4285 /*
4297 4286 * quiesce(9E) entry point.
4298 4287 *
4299 4288 * This function is called when the system is single-threaded at high
4300 4289 * PIL with preemption disabled. Therefore, this function must not be
4301 4290 * blocked.
4302 4291 *
4303 4292 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure.
4304 4293 * DDI_FAILURE indicates an error condition and should almost never happen.
4305 4294 */
4306 4295 int
4307 4296 mwl_quiesce(dev_info_t *dip)
4308 4297 {
4309 4298 struct mwl_softc *sc;
4310 4299
4311 4300 sc = ddi_get_soft_state(mwl_soft_state_p, ddi_get_instance(dip));
4312 4301 if (sc == NULL)
4313 4302 return (DDI_FAILURE);
4314 4303
4315 4304 #ifdef DEBUG
4316 4305 mwl_dbg_flags = 0;
4317 4306 #endif
4318 4307
4319 4308 /*
4320 4309 * No more blocking is allowed while we are in quiesce(9E) entry point
4321 4310 */
4322 4311 sc->sc_flags |= MWL_F_QUIESCE;
4323 4312
4324 4313 /*
4325 4314 * Disable all interrupts
4326 4315 */
4327 4316 mwl_stop(sc);
4328 4317 return (DDI_SUCCESS);
4329 4318 }
4330 4319
4331 4320 int
4332 4321 _init(void)
4333 4322 {
4334 4323 int status;
4335 4324
4336 4325 status = ddi_soft_state_init(&mwl_soft_state_p,
4337 4326 sizeof (struct mwl_softc), 1);
4338 4327 if (status != 0)
4339 4328 return (status);
4340 4329
4341 4330 mac_init_ops(&mwl_dev_ops, "mwl");
4342 4331 status = mod_install(&modlinkage);
4343 4332 if (status != 0) {
4344 4333 mac_fini_ops(&mwl_dev_ops);
4345 4334 ddi_soft_state_fini(&mwl_soft_state_p);
4346 4335 }
4347 4336 return (status);
4348 4337 }
4349 4338
4350 4339 int
4351 4340 _info(struct modinfo *modinfop)
4352 4341 {
4353 4342 return (mod_info(&modlinkage, modinfop));
4354 4343 }
4355 4344
4356 4345 int
4357 4346 _fini(void)
4358 4347 {
4359 4348 int status;
4360 4349
4361 4350 status = mod_remove(&modlinkage);
4362 4351 if (status == 0) {
4363 4352 mac_fini_ops(&mwl_dev_ops);
4364 4353 ddi_soft_state_fini(&mwl_soft_state_p);
4365 4354 }
4366 4355 return (status);
4367 4356 }
|
↓ open down ↓ |
2123 lines elided |
↑ open up ↑ |
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX