2481 default:
2482 break;
2483 }
2484 break;
2485 }
2486 default:
2487 return (B_FALSE);
2488 }
2489 return (B_TRUE);
2490 }
2491
2492 static int
2493 xgell_stats_get(queue_t *q, mblk_t *mp, caddr_t cp, cred_t *credp)
2494 {
2495 xgelldev_t *lldev = (xgelldev_t *)cp;
2496 xge_hal_status_e status;
2497 int count = 0, retsize;
2498 char *buf;
2499
2500 buf = kmem_alloc(XGELL_STATS_BUFSIZE, KM_SLEEP);
2501 if (buf == NULL) {
2502 return (ENOSPC);
2503 }
2504
2505 status = xge_hal_aux_stats_tmac_read(lldev->devh, XGELL_STATS_BUFSIZE,
2506 buf, &retsize);
2507 if (status != XGE_HAL_OK) {
2508 kmem_free(buf, XGELL_STATS_BUFSIZE);
2509 xge_debug_ll(XGE_ERR, "tmac_read(): status %d", status);
2510 return (EINVAL);
2511 }
2512 count += retsize;
2513
2514 status = xge_hal_aux_stats_rmac_read(lldev->devh,
2515 XGELL_STATS_BUFSIZE - count,
2516 buf+count, &retsize);
2517 if (status != XGE_HAL_OK) {
2518 kmem_free(buf, XGELL_STATS_BUFSIZE);
2519 xge_debug_ll(XGE_ERR, "rmac_read(): status %d", status);
2520 return (EINVAL);
2521 }
2522 count += retsize;
2523
2547 return (EINVAL);
2548 }
2549 count += retsize;
2550
2551 *(buf + count - 1) = '\0'; /* remove last '\n' */
2552 (void) mi_mpprintf(mp, "%s", buf);
2553 kmem_free(buf, XGELL_STATS_BUFSIZE);
2554
2555 return (0);
2556 }
2557
2558 static int
2559 xgell_pciconf_get(queue_t *q, mblk_t *mp, caddr_t cp, cred_t *credp)
2560 {
2561 xgelldev_t *lldev = (xgelldev_t *)cp;
2562 xge_hal_status_e status;
2563 int retsize;
2564 char *buf;
2565
2566 buf = kmem_alloc(XGELL_PCICONF_BUFSIZE, KM_SLEEP);
2567 if (buf == NULL) {
2568 return (ENOSPC);
2569 }
2570 status = xge_hal_aux_pci_config_read(lldev->devh, XGELL_PCICONF_BUFSIZE,
2571 buf, &retsize);
2572 if (status != XGE_HAL_OK) {
2573 kmem_free(buf, XGELL_PCICONF_BUFSIZE);
2574 xge_debug_ll(XGE_ERR, "pci_config_read(): status %d", status);
2575 return (EINVAL);
2576 }
2577 *(buf + retsize - 1) = '\0'; /* remove last '\n' */
2578 (void) mi_mpprintf(mp, "%s", buf);
2579 kmem_free(buf, XGELL_PCICONF_BUFSIZE);
2580
2581 return (0);
2582 }
2583
2584 static int
2585 xgell_about_get(queue_t *q, mblk_t *mp, caddr_t cp, cred_t *credp)
2586 {
2587 xgelldev_t *lldev = (xgelldev_t *)cp;
2588 xge_hal_status_e status;
2589 int retsize;
2590 char *buf;
2591
2592 buf = kmem_alloc(XGELL_ABOUT_BUFSIZE, KM_SLEEP);
2593 if (buf == NULL) {
2594 return (ENOSPC);
2595 }
2596 status = xge_hal_aux_about_read(lldev->devh, XGELL_ABOUT_BUFSIZE,
2597 buf, &retsize);
2598 if (status != XGE_HAL_OK) {
2599 kmem_free(buf, XGELL_ABOUT_BUFSIZE);
2600 xge_debug_ll(XGE_ERR, "about_read(): status %d", status);
2601 return (EINVAL);
2602 }
2603 *(buf + retsize - 1) = '\0'; /* remove last '\n' */
2604 (void) mi_mpprintf(mp, "%s", buf);
2605 kmem_free(buf, XGELL_ABOUT_BUFSIZE);
2606
2607 return (0);
2608 }
2609
2610 static unsigned long bar0_offset = 0x110; /* adapter_control */
2611
2612 static int
2613 xgell_bar0_get(queue_t *q, mblk_t *mp, caddr_t cp, cred_t *credp)
2614 {
2615 xgelldev_t *lldev = (xgelldev_t *)cp;
2616 xge_hal_status_e status;
2617 int retsize;
2618 char *buf;
2619
2620 buf = kmem_alloc(XGELL_IOCTL_BUFSIZE, KM_SLEEP);
2621 if (buf == NULL) {
2622 return (ENOSPC);
2623 }
2624 status = xge_hal_aux_bar0_read(lldev->devh, bar0_offset,
2625 XGELL_IOCTL_BUFSIZE, buf, &retsize);
2626 if (status != XGE_HAL_OK) {
2627 kmem_free(buf, XGELL_IOCTL_BUFSIZE);
2628 xge_debug_ll(XGE_ERR, "bar0_read(): status %d", status);
2629 return (EINVAL);
2630 }
2631 *(buf + retsize - 1) = '\0'; /* remove last '\n' */
2632 (void) mi_mpprintf(mp, "%s", buf);
2633 kmem_free(buf, XGELL_IOCTL_BUFSIZE);
2634
2635 return (0);
2636 }
2637
2638 static int
2639 xgell_bar0_set(queue_t *q, mblk_t *mp, char *value, caddr_t cp, cred_t *credp)
2640 {
2641 unsigned long old_offset = bar0_offset;
2642 char *end;
2643
2646 value += 2;
2647 }
2648
2649 bar0_offset = mi_strtol(value, &end, 16);
2650 if (end == value) {
2651 bar0_offset = old_offset;
2652 return (EINVAL);
2653 }
2654
2655 xge_debug_ll(XGE_TRACE, "bar0: new value %s:%lX", value, bar0_offset);
2656
2657 return (0);
2658 }
2659
2660 static int
2661 xgell_debug_level_get(queue_t *q, mblk_t *mp, caddr_t cp, cred_t *credp)
2662 {
2663 char *buf;
2664
2665 buf = kmem_alloc(XGELL_IOCTL_BUFSIZE, KM_SLEEP);
2666 if (buf == NULL) {
2667 return (ENOSPC);
2668 }
2669 (void) mi_mpprintf(mp, "debug_level %d", xge_hal_driver_debug_level());
2670 kmem_free(buf, XGELL_IOCTL_BUFSIZE);
2671
2672 return (0);
2673 }
2674
2675 static int
2676 xgell_debug_level_set(queue_t *q, mblk_t *mp, char *value, caddr_t cp,
2677 cred_t *credp)
2678 {
2679 int level;
2680 char *end;
2681
2682 level = mi_strtol(value, &end, 10);
2683 if (level < XGE_NONE || level > XGE_ERR || end == value) {
2684 return (EINVAL);
2685 }
2686
2687 xge_hal_driver_debug_level_set(level);
2688
2689 return (0);
2690 }
2691
2692 static int
2693 xgell_debug_module_mask_get(queue_t *q, mblk_t *mp, caddr_t cp, cred_t *credp)
2694 {
2695 char *buf;
2696
2697 buf = kmem_alloc(XGELL_IOCTL_BUFSIZE, KM_SLEEP);
2698 if (buf == NULL) {
2699 return (ENOSPC);
2700 }
2701 (void) mi_mpprintf(mp, "debug_module_mask 0x%08x",
2702 xge_hal_driver_debug_module_mask());
2703 kmem_free(buf, XGELL_IOCTL_BUFSIZE);
2704
2705 return (0);
2706 }
2707
2708 static int
2709 xgell_debug_module_mask_set(queue_t *q, mblk_t *mp, char *value, caddr_t cp,
2710 cred_t *credp)
2711 {
2712 u32 mask;
2713 char *end;
2714
2715 if (value && *value == '0' &&
2716 (*(value + 1) == 'x' || *(value + 1) == 'X')) {
2717 value += 2;
2718 }
2719
2720 mask = mi_strtol(value, &end, 16);
2721 if (end == value) {
2722 return (EINVAL);
2723 }
2724
2725 xge_hal_driver_debug_module_mask_set(mask);
2726
2727 return (0);
2728 }
2729
2730 static int
2731 xgell_devconfig_get(queue_t *q, mblk_t *mp, caddr_t cp, cred_t *credp)
2732 {
2733 xgelldev_t *lldev = (xgelldev_t *)(void *)cp;
2734 xge_hal_status_e status;
2735 int retsize;
2736 char *buf;
2737
2738 buf = kmem_alloc(XGELL_DEVCONF_BUFSIZE, KM_SLEEP);
2739 if (buf == NULL) {
2740 return (ENOSPC);
2741 }
2742 status = xge_hal_aux_device_config_read(lldev->devh,
2743 XGELL_DEVCONF_BUFSIZE, buf, &retsize);
2744 if (status != XGE_HAL_OK) {
2745 kmem_free(buf, XGELL_DEVCONF_BUFSIZE);
2746 xge_debug_ll(XGE_ERR, "device_config_read(): status %d",
2747 status);
2748 return (EINVAL);
2749 }
2750 *(buf + retsize - 1) = '\0'; /* remove last '\n' */
2751 (void) mi_mpprintf(mp, "%s", buf);
2752 kmem_free(buf, XGELL_DEVCONF_BUFSIZE);
2753
2754 return (0);
2755 }
2756
2757 /*
2758 * xgell_device_register
2759 * @devh: pointer on HAL device
2760 * @config: pointer on this network device configuration
2761 * @ll_out: output pointer. Will be assigned to valid LL device.
|
2481 default:
2482 break;
2483 }
2484 break;
2485 }
2486 default:
2487 return (B_FALSE);
2488 }
2489 return (B_TRUE);
2490 }
2491
2492 static int
2493 xgell_stats_get(queue_t *q, mblk_t *mp, caddr_t cp, cred_t *credp)
2494 {
2495 xgelldev_t *lldev = (xgelldev_t *)cp;
2496 xge_hal_status_e status;
2497 int count = 0, retsize;
2498 char *buf;
2499
2500 buf = kmem_alloc(XGELL_STATS_BUFSIZE, KM_SLEEP);
2501
2502 status = xge_hal_aux_stats_tmac_read(lldev->devh, XGELL_STATS_BUFSIZE,
2503 buf, &retsize);
2504 if (status != XGE_HAL_OK) {
2505 kmem_free(buf, XGELL_STATS_BUFSIZE);
2506 xge_debug_ll(XGE_ERR, "tmac_read(): status %d", status);
2507 return (EINVAL);
2508 }
2509 count += retsize;
2510
2511 status = xge_hal_aux_stats_rmac_read(lldev->devh,
2512 XGELL_STATS_BUFSIZE - count,
2513 buf+count, &retsize);
2514 if (status != XGE_HAL_OK) {
2515 kmem_free(buf, XGELL_STATS_BUFSIZE);
2516 xge_debug_ll(XGE_ERR, "rmac_read(): status %d", status);
2517 return (EINVAL);
2518 }
2519 count += retsize;
2520
2544 return (EINVAL);
2545 }
2546 count += retsize;
2547
2548 *(buf + count - 1) = '\0'; /* remove last '\n' */
2549 (void) mi_mpprintf(mp, "%s", buf);
2550 kmem_free(buf, XGELL_STATS_BUFSIZE);
2551
2552 return (0);
2553 }
2554
2555 static int
2556 xgell_pciconf_get(queue_t *q, mblk_t *mp, caddr_t cp, cred_t *credp)
2557 {
2558 xgelldev_t *lldev = (xgelldev_t *)cp;
2559 xge_hal_status_e status;
2560 int retsize;
2561 char *buf;
2562
2563 buf = kmem_alloc(XGELL_PCICONF_BUFSIZE, KM_SLEEP);
2564 status = xge_hal_aux_pci_config_read(lldev->devh, XGELL_PCICONF_BUFSIZE,
2565 buf, &retsize);
2566 if (status != XGE_HAL_OK) {
2567 kmem_free(buf, XGELL_PCICONF_BUFSIZE);
2568 xge_debug_ll(XGE_ERR, "pci_config_read(): status %d", status);
2569 return (EINVAL);
2570 }
2571 *(buf + retsize - 1) = '\0'; /* remove last '\n' */
2572 (void) mi_mpprintf(mp, "%s", buf);
2573 kmem_free(buf, XGELL_PCICONF_BUFSIZE);
2574
2575 return (0);
2576 }
2577
2578 static int
2579 xgell_about_get(queue_t *q, mblk_t *mp, caddr_t cp, cred_t *credp)
2580 {
2581 xgelldev_t *lldev = (xgelldev_t *)cp;
2582 xge_hal_status_e status;
2583 int retsize;
2584 char *buf;
2585
2586 buf = kmem_alloc(XGELL_ABOUT_BUFSIZE, KM_SLEEP);
2587 status = xge_hal_aux_about_read(lldev->devh, XGELL_ABOUT_BUFSIZE,
2588 buf, &retsize);
2589 if (status != XGE_HAL_OK) {
2590 kmem_free(buf, XGELL_ABOUT_BUFSIZE);
2591 xge_debug_ll(XGE_ERR, "about_read(): status %d", status);
2592 return (EINVAL);
2593 }
2594 *(buf + retsize - 1) = '\0'; /* remove last '\n' */
2595 (void) mi_mpprintf(mp, "%s", buf);
2596 kmem_free(buf, XGELL_ABOUT_BUFSIZE);
2597
2598 return (0);
2599 }
2600
2601 static unsigned long bar0_offset = 0x110; /* adapter_control */
2602
2603 static int
2604 xgell_bar0_get(queue_t *q, mblk_t *mp, caddr_t cp, cred_t *credp)
2605 {
2606 xgelldev_t *lldev = (xgelldev_t *)cp;
2607 xge_hal_status_e status;
2608 int retsize;
2609 char *buf;
2610
2611 buf = kmem_alloc(XGELL_IOCTL_BUFSIZE, KM_SLEEP);
2612 status = xge_hal_aux_bar0_read(lldev->devh, bar0_offset,
2613 XGELL_IOCTL_BUFSIZE, buf, &retsize);
2614 if (status != XGE_HAL_OK) {
2615 kmem_free(buf, XGELL_IOCTL_BUFSIZE);
2616 xge_debug_ll(XGE_ERR, "bar0_read(): status %d", status);
2617 return (EINVAL);
2618 }
2619 *(buf + retsize - 1) = '\0'; /* remove last '\n' */
2620 (void) mi_mpprintf(mp, "%s", buf);
2621 kmem_free(buf, XGELL_IOCTL_BUFSIZE);
2622
2623 return (0);
2624 }
2625
2626 static int
2627 xgell_bar0_set(queue_t *q, mblk_t *mp, char *value, caddr_t cp, cred_t *credp)
2628 {
2629 unsigned long old_offset = bar0_offset;
2630 char *end;
2631
2634 value += 2;
2635 }
2636
2637 bar0_offset = mi_strtol(value, &end, 16);
2638 if (end == value) {
2639 bar0_offset = old_offset;
2640 return (EINVAL);
2641 }
2642
2643 xge_debug_ll(XGE_TRACE, "bar0: new value %s:%lX", value, bar0_offset);
2644
2645 return (0);
2646 }
2647
2648 static int
2649 xgell_debug_level_get(queue_t *q, mblk_t *mp, caddr_t cp, cred_t *credp)
2650 {
2651 char *buf;
2652
2653 buf = kmem_alloc(XGELL_IOCTL_BUFSIZE, KM_SLEEP);
2654 (void) mi_mpprintf(mp, "debug_level %d", xge_hal_driver_debug_level());
2655 kmem_free(buf, XGELL_IOCTL_BUFSIZE);
2656
2657 return (0);
2658 }
2659
2660 static int
2661 xgell_debug_level_set(queue_t *q, mblk_t *mp, char *value, caddr_t cp,
2662 cred_t *credp)
2663 {
2664 int level;
2665 char *end;
2666
2667 level = mi_strtol(value, &end, 10);
2668 if (level < XGE_NONE || level > XGE_ERR || end == value) {
2669 return (EINVAL);
2670 }
2671
2672 xge_hal_driver_debug_level_set(level);
2673
2674 return (0);
2675 }
2676
2677 static int
2678 xgell_debug_module_mask_get(queue_t *q, mblk_t *mp, caddr_t cp, cred_t *credp)
2679 {
2680 char *buf;
2681
2682 buf = kmem_alloc(XGELL_IOCTL_BUFSIZE, KM_SLEEP);
2683 (void) mi_mpprintf(mp, "debug_module_mask 0x%08x",
2684 xge_hal_driver_debug_module_mask());
2685 kmem_free(buf, XGELL_IOCTL_BUFSIZE);
2686
2687 return (0);
2688 }
2689
2690 static int
2691 xgell_debug_module_mask_set(queue_t *q, mblk_t *mp, char *value, caddr_t cp,
2692 cred_t *credp)
2693 {
2694 u32 mask;
2695 char *end;
2696
2697 if (value && *value == '0' &&
2698 (*(value + 1) == 'x' || *(value + 1) == 'X')) {
2699 value += 2;
2700 }
2701
2702 mask = mi_strtol(value, &end, 16);
2703 if (end == value) {
2704 return (EINVAL);
2705 }
2706
2707 xge_hal_driver_debug_module_mask_set(mask);
2708
2709 return (0);
2710 }
2711
2712 static int
2713 xgell_devconfig_get(queue_t *q, mblk_t *mp, caddr_t cp, cred_t *credp)
2714 {
2715 xgelldev_t *lldev = (xgelldev_t *)(void *)cp;
2716 xge_hal_status_e status;
2717 int retsize;
2718 char *buf;
2719
2720 buf = kmem_alloc(XGELL_DEVCONF_BUFSIZE, KM_SLEEP);
2721 status = xge_hal_aux_device_config_read(lldev->devh,
2722 XGELL_DEVCONF_BUFSIZE, buf, &retsize);
2723 if (status != XGE_HAL_OK) {
2724 kmem_free(buf, XGELL_DEVCONF_BUFSIZE);
2725 xge_debug_ll(XGE_ERR, "device_config_read(): status %d",
2726 status);
2727 return (EINVAL);
2728 }
2729 *(buf + retsize - 1) = '\0'; /* remove last '\n' */
2730 (void) mi_mpprintf(mp, "%s", buf);
2731 kmem_free(buf, XGELL_DEVCONF_BUFSIZE);
2732
2733 return (0);
2734 }
2735
2736 /*
2737 * xgell_device_register
2738 * @devh: pointer on HAL device
2739 * @config: pointer on this network device configuration
2740 * @ll_out: output pointer. Will be assigned to valid LL device.
|