448 /*
449 * The kpm mapping window.
450 * kpm_size:
451 * The size of a single kpm range.
452 * The overall size will be: kpm_size * vac_colors.
453 * kpm_vbase:
454 * The virtual start address of the kpm range within the kernel
455 * virtual address space. kpm_vbase has to be kpm_size aligned.
456 */
457
458 /*
459 * Make kpm_vbase, kpm_size aligned to kpm_size_shift.
460 * To do this find the nearest power of 2 size that the
461 * actual ra_limit fits within.
462 * If it is an even power of two use that, otherwise use the
463 * next power of two larger than ra_limit.
464 */
465
466 ASSERT(ra_limit != 0);
467
468 kpm_size_shift = (ra_limit & (ra_limit - 1)) != 0 ?
469 highbit(ra_limit) : highbit(ra_limit) - 1;
470
471 /*
472 * No virtual caches on sun4v so size matches size shift
473 */
474 kpm_size = 1ul << kpm_size_shift;
475
476 if (va_bits < VA_ADDRESS_SPACE_BITS) {
477 /*
478 * In case of VA hole
479 * kpm_base = hole_end + 1TB
480 * Starting 1TB beyond where VA hole ends because on Niagara
481 * processor software must not use pages within 4GB of the
482 * VA hole as instruction pages to avoid problems with
483 * prefetching into the VA hole.
484 */
485 kpm_vbase = (caddr_t)((0ull - (1ull << (va_bits - 1))) +
486 (1ull << 40));
487 } else { /* Number of VA bits 64 ... no VA hole */
488 kpm_vbase = (caddr_t)0x8000000000000000ull; /* 8 EB */
833 get_single_q_size(md_t *mdp, mde_cookie_t cpu_node_cookie,
834 char *qnamep, uint64_t default_entries, uint64_t max_entries)
835 {
836 uint64_t entries;
837
838 if (default_entries > max_entries)
839 cmn_err(CE_CONT, "!get_single_q_size: dflt %ld > "
840 "max %ld for %s\n", default_entries, max_entries, qnamep);
841
842 if (md_get_prop_val(mdp, cpu_node_cookie, qnamep, &entries)) {
843 if (!broken_md_flag)
844 cmn_err(CE_PANIC, "Missing %s property in MD cpu node",
845 qnamep);
846 entries = default_entries;
847 } else {
848 entries = 1 << entries;
849 }
850
851 entries = MIN(entries, max_entries);
852 /* If not a power of 2, truncate to a power of 2. */
853 if ((entries & (entries - 1)) != 0) {
854 entries = 1 << (highbit(entries) - 1);
855 }
856
857 return (entries);
858 }
859
860 /* Scaling constant used to compute size of cpu mondo queue */
861 #define CPU_MONDO_Q_MULTIPLIER 8
862
863 static void
864 get_q_sizes(md_t *mdp, mde_cookie_t cpu_node_cookie)
865 {
866 uint64_t max_qsize;
867 mde_cookie_t *platlist;
868 int nrnode;
869
870 /*
871 * Compute the maximum number of entries for the cpu mondo queue.
872 * Use the appropriate property in the platform node, if it is
873 * available. Else, base it on NCPU.
|
448 /*
449 * The kpm mapping window.
450 * kpm_size:
451 * The size of a single kpm range.
452 * The overall size will be: kpm_size * vac_colors.
453 * kpm_vbase:
454 * The virtual start address of the kpm range within the kernel
455 * virtual address space. kpm_vbase has to be kpm_size aligned.
456 */
457
458 /*
459 * Make kpm_vbase, kpm_size aligned to kpm_size_shift.
460 * To do this find the nearest power of 2 size that the
461 * actual ra_limit fits within.
462 * If it is an even power of two use that, otherwise use the
463 * next power of two larger than ra_limit.
464 */
465
466 ASSERT(ra_limit != 0);
467
468 kpm_size_shift = !ISP2(ra_limit) ?
469 highbit(ra_limit) : highbit(ra_limit) - 1;
470
471 /*
472 * No virtual caches on sun4v so size matches size shift
473 */
474 kpm_size = 1ul << kpm_size_shift;
475
476 if (va_bits < VA_ADDRESS_SPACE_BITS) {
477 /*
478 * In case of VA hole
479 * kpm_base = hole_end + 1TB
480 * Starting 1TB beyond where VA hole ends because on Niagara
481 * processor software must not use pages within 4GB of the
482 * VA hole as instruction pages to avoid problems with
483 * prefetching into the VA hole.
484 */
485 kpm_vbase = (caddr_t)((0ull - (1ull << (va_bits - 1))) +
486 (1ull << 40));
487 } else { /* Number of VA bits 64 ... no VA hole */
488 kpm_vbase = (caddr_t)0x8000000000000000ull; /* 8 EB */
833 get_single_q_size(md_t *mdp, mde_cookie_t cpu_node_cookie,
834 char *qnamep, uint64_t default_entries, uint64_t max_entries)
835 {
836 uint64_t entries;
837
838 if (default_entries > max_entries)
839 cmn_err(CE_CONT, "!get_single_q_size: dflt %ld > "
840 "max %ld for %s\n", default_entries, max_entries, qnamep);
841
842 if (md_get_prop_val(mdp, cpu_node_cookie, qnamep, &entries)) {
843 if (!broken_md_flag)
844 cmn_err(CE_PANIC, "Missing %s property in MD cpu node",
845 qnamep);
846 entries = default_entries;
847 } else {
848 entries = 1 << entries;
849 }
850
851 entries = MIN(entries, max_entries);
852 /* If not a power of 2, truncate to a power of 2. */
853 if (!ISP2(entries)) {
854 entries = 1 << (highbit(entries) - 1);
855 }
856
857 return (entries);
858 }
859
860 /* Scaling constant used to compute size of cpu mondo queue */
861 #define CPU_MONDO_Q_MULTIPLIER 8
862
863 static void
864 get_q_sizes(md_t *mdp, mde_cookie_t cpu_node_cookie)
865 {
866 uint64_t max_qsize;
867 mde_cookie_t *platlist;
868 int nrnode;
869
870 /*
871 * Compute the maximum number of entries for the cpu mondo queue.
872 * Use the appropriate property in the platform node, if it is
873 * available. Else, base it on NCPU.
|