182 "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu"
183
184 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */
185 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */
186 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */
187 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */
188 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */
189 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */
190 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */
191 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */
192 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */
193 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */
194 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */
195 #define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: SSE5 */
196 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */
197 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */
198 #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */
199
200 #define FMT_CPUID_AMD_ECX \
201 "\20" \
202 "\22topoext" \
203 "\14wdt\13skinit\12sse5\11ibs\10osvw\93dnp\8mas" \
204 "\7sse4a\6lzcnt\5cr8d\3svm\2lcmplgcy\1ahf64"
205
206 /*
207 * Intel now seems to have claimed part of the "extended" function
208 * space that we previously for non-Intel implementors to use.
209 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF
210 * is available in long mode i.e. what AMD indicate using bit 0.
211 * On the other hand, everything else is labelled as reserved.
212 */
213 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */
214
215 /*
216 * Intel also uses cpuid leaf 7 to have additional instructions and features.
217 * Like some other leaves, but unlike the current ones we care about, it
218 * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal
219 * with the potential use of additional sub-leaves in the future, we now
220 * specifically label the EBX features with their leaf and sub-leaf.
221 */
222 #define CPUID_INTC_EBX_7_0_BMI1 0x00000008 /* BMI1 instrs */
223 #define CPUID_INTC_EBX_7_0_AVX2 0x00000020 /* AVX2 supported */
|
182 "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu"
183
184 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */
185 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */
186 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */
187 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */
188 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */
189 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */
190 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */
191 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */
192 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */
193 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */
194 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */
195 #define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: SSE5 */
196 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */
197 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */
198 #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */
199
200 #define FMT_CPUID_AMD_ECX \
201 "\20" \
202 "\27topoext" \
203 "\16wdt\15skinit\14sse5\13ibs\12osvw\0113dnp\10mas" \
204 "\7sse4a\6lzcnt\5cr8d\3svm\2lcmplgcy\1ahf64"
205
206 /*
207 * Intel now seems to have claimed part of the "extended" function
208 * space that we previously for non-Intel implementors to use.
209 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF
210 * is available in long mode i.e. what AMD indicate using bit 0.
211 * On the other hand, everything else is labelled as reserved.
212 */
213 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */
214
215 /*
216 * Intel also uses cpuid leaf 7 to have additional instructions and features.
217 * Like some other leaves, but unlike the current ones we care about, it
218 * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal
219 * with the potential use of additional sub-leaves in the future, we now
220 * specifically label the EBX features with their leaf and sub-leaf.
221 */
222 #define CPUID_INTC_EBX_7_0_BMI1 0x00000008 /* BMI1 instrs */
223 #define CPUID_INTC_EBX_7_0_AVX2 0x00000020 /* AVX2 supported */
|