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XXXX define x2apic feature flag

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          --- old/usr/src/uts/intel/sys/x86_archext.h
          +++ new/usr/src/uts/intel/sys/x86_archext.h
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 109  109                                                  /* 0x00000800 - reserved */
 110  110                                                  /* 0x00001000 - reserved */
 111  111  #define CPUID_INTC_ECX_CX16     0x00002000      /* cmpxchg16 */
 112  112  #define CPUID_INTC_ECX_ETPRD    0x00004000      /* extended task pri messages */
 113  113                                                  /* 0x00008000 - reserved */
 114  114                                                  /* 0x00010000 - reserved */
 115  115                                                  /* 0x00020000 - reserved */
 116  116  #define CPUID_INTC_ECX_DCA      0x00040000      /* direct cache access */
 117  117  #define CPUID_INTC_ECX_SSE4_1   0x00080000      /* SSE4.1 insns */
 118  118  #define CPUID_INTC_ECX_SSE4_2   0x00100000      /* SSE4.2 insns */
      119 +#define CPUID_INTC_ECX_X2APIC   0x00200000      /* x2APIC */
 119  120  #define CPUID_INTC_ECX_MOVBE    0x00400000      /* MOVBE insn */
 120  121  #define CPUID_INTC_ECX_POPCNT   0x00800000      /* POPCNT insn */
 121  122  #define CPUID_INTC_ECX_AES      0x02000000      /* AES insns */
 122  123  #define CPUID_INTC_ECX_XSAVE    0x04000000      /* XSAVE/XRESTOR insns */
 123  124  #define CPUID_INTC_ECX_OSXSAVE  0x08000000      /* OS supports XSAVE insns */
 124  125  #define CPUID_INTC_ECX_AVX      0x10000000      /* AVX supported */
 125  126  #define CPUID_INTC_ECX_F16C     0x20000000      /* F16C supported */
 126  127  #define CPUID_INTC_ECX_RDRAND   0x40000000      /* RDRAND supported */
 127  128  #define CPUID_INTC_ECX_HV       0x80000000      /* Hypervisor */
 128  129  
 129  130  #define FMT_CPUID_INTC_ECX                                      \
 130  131          "\20"                                                   \
 131  132          "\37rdrand\36f16c\35avx\34osxsav\33xsave"               \
 132  133          "\32aes"                                                \
 133      -        "\30popcnt\27movbe\25sse4.2\24sse4.1\23dca"             \
      134 +        "\30popcnt\27movbe\26x2apic\25sse4.2\24sse4.1\23dca"    \
 134  135          "\20\17etprd\16cx16\13cid\12ssse3\11tm2"                \
 135  136          "\10est\7smx\6vmx\5dscpl\4mon\2pclmulqdq\1sse3"
 136  137  
 137  138  /*
 138  139   * cpuid instruction feature flags in %edx (extended function 0x80000001)
 139  140   */
 140  141  
 141  142  #define CPUID_AMD_EDX_FPU       0x00000001      /* x87 fpu present */
 142  143  #define CPUID_AMD_EDX_VME       0x00000002      /* virtual-8086 extension */
 143  144  #define CPUID_AMD_EDX_DE        0x00000004      /* debugging extensions */
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 339  340          ((uint64_t)MTRR_TYPE_WC << 48) |        \
 340  341          ((uint64_t)MTRR_TYPE_UC << 56))
 341  342  
 342  343  #define X86FSET_LARGEPAGE       0
 343  344  #define X86FSET_TSC             1
 344  345  #define X86FSET_MSR             2
 345  346  #define X86FSET_MTRR            3
 346  347  #define X86FSET_PGE             4
 347  348  #define X86FSET_DE              5
 348  349  #define X86FSET_CMOV            6
 349      -#define X86FSET_MMX             7
      350 +#define X86FSET_MMX             7
 350  351  #define X86FSET_MCA             8
 351  352  #define X86FSET_PAE             9
 352  353  #define X86FSET_CX8             10
 353  354  #define X86FSET_PAT             11
 354  355  #define X86FSET_SEP             12
 355  356  #define X86FSET_SSE             13
 356  357  #define X86FSET_SSE2            14
 357  358  #define X86FSET_HTT             15
 358  359  #define X86FSET_ASYSC           16
 359  360  #define X86FSET_NX              17
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 372  373  #define X86FSET_64              30
 373  374  #define X86FSET_AES             31
 374  375  #define X86FSET_PCLMULQDQ       32
 375  376  #define X86FSET_XSAVE           33
 376  377  #define X86FSET_AVX             34
 377  378  #define X86FSET_VMX             35
 378  379  #define X86FSET_SVM             36
 379  380  #define X86FSET_TOPOEXT         37
 380  381  #define X86FSET_F16C            38
 381  382  #define X86FSET_RDRAND          39
      383 +#define X86FSET_X2APIC          40
 382  384  
 383  385  /*
 384  386   * flags to patch tsc_read routine.
 385  387   */
 386  388  #define X86_NO_TSC              0x0
 387  389  #define X86_HAVE_TSCP           0x1
 388  390  #define X86_TSC_MFENCE          0x2
 389  391  #define X86_TSC_LFENCE          0x4
 390  392  
 391  393  /*
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 632  634  #define XFEATURE_SSE            0x2
 633  635  #define XFEATURE_AVX            0x4
 634  636  #define XFEATURE_MAX            XFEATURE_AVX
 635  637  #define XFEATURE_FP_ALL \
 636  638          (XFEATURE_LEGACY_FP|XFEATURE_SSE|XFEATURE_AVX)
 637  639  
 638  640  #if !defined(_ASM)
 639  641  
 640  642  #if defined(_KERNEL) || defined(_KMEMUSER)
 641  643  
 642      -#define NUM_X86_FEATURES        40
      644 +#define NUM_X86_FEATURES        41
 643  645  extern uchar_t x86_featureset[];
 644  646  
 645  647  extern void free_x86_featureset(void *featureset);
 646  648  extern boolean_t is_x86_feature(void *featureset, uint_t feature);
 647  649  extern void add_x86_feature(void *featureset, uint_t feature);
 648  650  extern void remove_x86_feature(void *featureset, uint_t feature);
 649  651  extern boolean_t compare_x86_featureset(void *setA, void *setB);
 650  652  extern void print_x86_featureset(void *featureset);
 651  653  
 652  654  
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