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--- old/usr/src/uts/i86pc/sys/apic.h
+++ new/usr/src/uts/i86pc/sys/apic.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved.
23 23 */
24 24
25 25 /*
26 26 * Copyright (c) 2010, Intel Corporation.
27 27 * All rights reserved.
28 28 */
29 29
30 30 #ifndef _SYS_APIC_APIC_H
31 31 #define _SYS_APIC_APIC_H
32 32
33 33 #include <sys/psm_types.h>
34 34 #include <sys/avintr.h>
35 35 #include <sys/pci.h>
36 36
37 37 #ifdef __cplusplus
38 38 extern "C" {
39 39 #endif
40 40
41 41 #include <sys/psm_common.h>
42 42
43 43 #define APIC_PCPLUSMP_NAME "pcplusmp"
44 44 #define APIC_APIX_NAME "apix"
45 45
46 46 #define APIC_IO_ADDR 0xfec00000
47 47 #define APIC_LOCAL_ADDR 0xfee00000
48 48 #define APIC_IO_MEMLEN 0xf
49 49 #define APIC_LOCAL_MEMLEN 0xfffff
50 50
51 51 /* Local Unit ID register */
52 52 #define APIC_LID_REG 0x8
53 53
54 54 /* I/o Unit Version Register */
55 55 #define APIC_VERS_REG 0xc
56 56
57 57 /* Task Priority register */
58 58 #define APIC_TASK_REG 0x20
59 59
60 60 /* EOI register */
61 61 #define APIC_EOI_REG 0x2c
62 62
63 63 /* Remote Read register */
64 64 #define APIC_REMOTE_READ 0x30
65 65
66 66 /* Logical Destination register */
67 67 #define APIC_DEST_REG 0x34
68 68
69 69 /* Destination Format register */
70 70 #define APIC_FORMAT_REG 0x38
71 71
72 72 /* Spurious Interrupt Vector register */
73 73 #define APIC_SPUR_INT_REG 0x3c
74 74
75 75 /* Error Status Register */
76 76 #define APIC_ERROR_STATUS 0xa0
77 77
78 78 /* Interrupt Command registers */
79 79 #define APIC_INT_CMD1 0xc0
80 80 #define APIC_INT_CMD2 0xc4
81 81
82 82 /* Local Interrupt Vector registers */
83 83 #define APIC_CMCI_VECT 0xbc
84 84 #define APIC_THERM_VECT 0xcc
85 85 #define APIC_PCINT_VECT 0xd0
86 86 #define APIC_INT_VECT0 0xd4
87 87 #define APIC_INT_VECT1 0xd8
88 88 #define APIC_ERR_VECT 0xdc
89 89
90 90 /* IPL for performance counter interrupts */
91 91 #define APIC_PCINT_IPL 0xe
92 92 #define APIC_LVT_MASK 0x10000 /* Mask bit (16) in LVT */
93 93
94 94 /* Initial Count register */
95 95 #define APIC_INIT_COUNT 0xe0
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95 lines elided |
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96 96
97 97 /* Current Count Register */
98 98 #define APIC_CURR_COUNT 0xe4
99 99 #define APIC_CURR_ADD 0x39 /* used for remote read command */
100 100 #define CURR_COUNT_OFFSET (sizeof (int32_t) * APIC_CURR_COUNT)
101 101
102 102 /* Divider Configuration Register */
103 103 #define APIC_DIVIDE_REG 0xf8
104 104
105 105 /* Various mode for local APIC. Modes are mutually exclusive */
106 -#define APIC_IS_DISABLED 0x0
107 -#define APIC_MODE_NOTSET 0x1
108 -#define LOCAL_APIC 0x2
109 -#define LOCAL_X2APIC 0x3
106 +enum apic_mode {
107 + APIC_IS_DISABLED,
108 + APIC_MODE_NOTSET,
109 + LOCAL_APIC,
110 + LOCAL_X2APIC,
111 +};
110 112
111 113 /* x2APIC SELF IPI Register */
112 114 #define X2APIC_SELF_IPI 0xFC
113 115
114 116 /* General x2APIC constants used at various places */
115 117 #define APIC_SVR_SUPPRESS_BROADCAST_EOI 0x1000
116 118 #define APIC_DIRECTED_EOI_BIT 0x1000000
117 119
118 120 /* IRR register */
119 121 #define APIC_IRR_REG 0x80
120 122
121 123 /* ISR register */
122 124 #define APIC_ISR_REG 0x40
123 125
124 126 #define APIC_IO_REG 0x0
125 127 #define APIC_IO_DATA 0x4
126 128 #define APIC_IO_EOI 0x10
127 129
128 130 /* Bit offset of APIC ID in LID_REG, INT_CMD and in DEST_REG */
129 131 #define APIC_ID_BIT_OFFSET 24
130 132 #define APIC_ICR_ID_BIT_OFFSET 24
131 133 #define APIC_LDR_ID_BIT_OFFSET 24
132 134
133 135 /*
134 136 * Choose between flat and clustered models by writing the following to the
135 137 * FORMAT_REG. 82489 DX documentation seemed to suggest that writing 0 will
136 138 * disable logical destination mode.
137 139 * Does not seem to be in the docs for local APICs on the processors.
138 140 */
139 141 #define APIC_FLAT_MODEL 0xFFFFFFFFUL
140 142 #define APIC_CLUSTER_MODEL 0x0FFFFFFF
141 143
142 144 /*
143 145 * The commands which follow are window selectors written to APIC_IO_REG
144 146 * before data can be read/written from/to APIC_IO_DATA
145 147 */
146 148
147 149 #define APIC_ID_CMD 0x0
148 150 #define APIC_VERS_CMD 0x1
149 151 #define APIC_RDT_CMD 0x10
150 152 #define APIC_RDT_CMD2 0x11
151 153
152 154 #define APIC_INTEGRATED_VERS 0x10 /* 0x10 & above indicates integrated */
153 155 #define IOAPIC_VER_82489DX 0x01 /* Version ID: 82489DX External APIC */
154 156
155 157 #define APIC_INT_SPURIOUS -1
156 158
157 159 #define APIC_IMCR_P1 0x22 /* int mode conf register port 1 */
158 160 #define APIC_IMCR_P2 0x23 /* int mode conf register port 2 */
159 161 #define APIC_IMCR_SELECT 0x70 /* select imcr by writing into P1 */
160 162 #define APIC_IMCR_PIC 0x0 /* selects PIC mode (8259-> BSP) */
161 163 #define APIC_IMCR_APIC 0x1 /* selects APIC mode (8259->APIC) */
162 164
163 165 #define APIC_CT_VECT 0x4ac /* conf table vector */
164 166 #define APIC_CT_SIZE 1024 /* conf table size */
165 167
166 168 #define APIC_ID 'MPAT' /* conf table signature */
167 169
168 170 #define VENID_AMD 0x1022
169 171 #define DEVID_8131_IOAPIC 0x7451
170 172 #define DEVID_8132_IOAPIC 0x7459
171 173
172 174 #define IOAPICS_NODE_NAME "ioapics"
173 175 #define IOAPICS_CHILD_NAME "ioapic"
174 176 #define IOAPICS_DEV_TYPE "ioapic"
175 177 #define IOAPICS_PROP_VENID "vendor-id"
176 178 #define IOAPICS_PROP_DEVID "device-id"
177 179
178 180 #define IS_CLASS_IOAPIC(b, s, p) \
179 181 ((b) == PCI_CLASS_PERIPH && (s) == PCI_PERIPH_PIC && \
180 182 ((p) == PCI_PERIPH_PIC_IF_IO_APIC || \
181 183 (p) == PCI_PERIPH_PIC_IF_IOX_APIC))
182 184
183 185 /*
184 186 * These macros are used in frequently called routines like
185 187 * apic_intr_enter().
186 188 */
187 189 #define X2APIC_WRITE(reg, v) \
188 190 wrmsr((REG_X2APIC_BASE_MSR + (reg >> 2)), v)
189 191
190 192 #define LOCAL_APIC_WRITE_REG(reg, v) \
191 193 apicadr[reg] = v
192 194
193 195 /*
194 196 * MP floating pointer structure defined in Intel MP Spec 1.1
195 197 */
196 198 struct apic_mpfps_hdr {
197 199 uint32_t mpfps_sig; /* _MP_ (0x5F4D505F) */
198 200 uint32_t mpfps_mpct_paddr; /* paddr of MP configuration tbl */
199 201 uchar_t mpfps_length; /* in paragraph (16-bytes units) */
200 202 uchar_t mpfps_spec_rev; /* version number of MP spec */
201 203 uchar_t mpfps_checksum; /* checksum of complete structure */
202 204 uchar_t mpfps_featinfo1; /* mp feature info bytes 1 */
203 205 uchar_t mpfps_featinfo2; /* mp feature info bytes 2 */
204 206 uchar_t mpfps_featinfo3; /* mp feature info bytes 3 */
205 207 uchar_t mpfps_featinfo4; /* mp feature info bytes 4 */
206 208 uchar_t mpfps_featinfo5; /* mp feature info bytes 5 */
207 209 };
208 210
209 211 #define MPFPS_FEATINFO2_IMCRP 0x80 /* IMCRP presence bit */
210 212
211 213 #define APIC_MPS_OEM_ID_LEN 8
212 214 #define APIC_MPS_PROD_ID_LEN 12
213 215
214 216 struct apic_mp_cnf_hdr {
215 217 uint_t mpcnf_sig;
216 218
217 219 uint_t mpcnf_tbl_length: 16,
218 220 mpcnf_spec: 8,
219 221 mpcnf_cksum: 8;
220 222
221 223 char mpcnf_oem_str[APIC_MPS_OEM_ID_LEN];
222 224
223 225 char mpcnf_prod_str[APIC_MPS_PROD_ID_LEN];
224 226
225 227 uint_t mpcnf_oem_ptr;
226 228
227 229 uint_t mpcnf_oem_tbl_size: 16,
228 230 mpcnf_entry_cnt: 16;
229 231
230 232 uint_t mpcnf_local_apic;
231 233
232 234 uint_t mpcnf_resv;
233 235 };
234 236
235 237 struct apic_procent {
236 238 uint_t proc_entry: 8,
237 239 proc_apicid: 8,
238 240 proc_version: 8,
239 241 proc_cpuflags: 8;
240 242
241 243 uint_t proc_stepping: 4,
242 244 proc_model: 4,
243 245 proc_family: 4,
244 246 proc_type: 2, /* undocumented feature */
245 247 proc_resv1: 18;
246 248
247 249 uint_t proc_feature;
248 250
249 251 uint_t proc_resv2;
250 252
251 253 uint_t proc_resv3;
252 254 };
253 255
254 256 /*
255 257 * proc_cpuflags definitions
256 258 */
257 259 #define CPUFLAGS_EN 1 /* if not set, this processor is unusable */
258 260 #define CPUFLAGS_BP 2 /* set if this is the bootstrap processor */
259 261
260 262
261 263 struct apic_bus {
262 264 uchar_t bus_entry;
263 265 uchar_t bus_id;
264 266 ushort_t bus_str1;
265 267 uint_t bus_str2;
266 268 };
267 269
268 270 struct apic_io_entry {
269 271 uint_t io_entry: 8,
270 272 io_apicid: 8,
271 273 io_version: 8,
272 274 io_flags: 8;
273 275
274 276 uint_t io_apic_addr;
275 277 };
276 278
277 279 #define IOAPIC_FLAGS_EN 0x01 /* this I/O apic is enable or not */
278 280
279 281 #define MAX_IO_APIC 32 /* maximum # of IOAPICs supported */
280 282
281 283 struct apic_io_intr {
282 284 uint_t intr_entry: 8,
283 285 intr_type: 8,
284 286 intr_po: 2,
285 287 intr_el: 2,
286 288 intr_resv: 12;
287 289
288 290 uint_t intr_busid: 8,
289 291 intr_irq: 8,
290 292 intr_destid: 8,
291 293 intr_destintin: 8;
292 294 };
293 295
294 296 /*
295 297 * intr_type definitions
296 298 */
297 299 #define IO_INTR_INT 0x00
298 300 #define IO_INTR_NMI 0x01
299 301 #define IO_INTR_SMI 0x02
300 302 #define IO_INTR_EXTINT 0x03
301 303
302 304 /*
303 305 * destination APIC ID
304 306 */
305 307 #define INTR_ALL_APIC 0xff
306 308
307 309
308 310 /* local vector table */
309 311 #define AV_MASK 0x10000
310 312
311 313 /* interrupt command register 32-63 */
312 314 #define AV_TOALL 0x7fffffff
313 315 #define AV_HIGH_ORDER 0x40000000
314 316 #define AV_IM_OFF 0x40000000
315 317
316 318 /* interrupt command register 0-31 */
317 319 #define AV_DELIV_MODE 0x700
318 320
319 321 #define AV_FIXED 0x000
320 322 #define AV_LOPRI 0x100
321 323 #define AV_SMI 0x200
322 324 #define AV_REMOTE 0x300
323 325 #define AV_NMI 0x400
324 326 #define AV_RESET 0x500
325 327 #define AV_STARTUP 0x600
326 328 #define AV_EXTINT 0x700
327 329
328 330 #define AV_PDEST 0x000
329 331 #define AV_LDEST 0x800
330 332
331 333 /* IO & Local APIC Bit Definitions */
332 334 #define RDT_VECTOR(x) ((uchar_t)((x) & 0xFF))
333 335 #define AV_PENDING 0x1000
334 336 #define AV_ACTIVE_LOW 0x2000 /* only for integrated APIC */
335 337 #define AV_REMOTE_IRR 0x4000 /* IOAPIC RDT-specific */
336 338 #define AV_LEVEL 0x8000
337 339 #define AV_DEASSERT AV_LEVEL
338 340 #define AV_ASSERT 0xc000
339 341
340 342 #define AV_READ_PENDING 0x10000
341 343 #define AV_REMOTE_STATUS 0x20000 /* 1 = valid, 0 = invalid */
342 344
343 345 #define AV_SH_SELF 0x40000 /* Short hand for self */
344 346 #define AV_SH_ALL_INCSELF 0x80000 /* All processors */
345 347 #define AV_SH_ALL_EXCSELF 0xc0000 /* All excluding self */
346 348 /* spurious interrupt vector register */
347 349 #define AV_UNIT_ENABLE 0x100
348 350
349 351 #define APIC_MAXVAL 0xffffffffUL
350 352 #define APIC_TIME_MIN 0x5000
351 353 #define APIC_TIME_COUNT 0x4000
352 354
353 355 /*
354 356 * Range of the low byte value in apic_tick before starting calibration
355 357 */
356 358 #define APIC_LB_MIN 0x60
357 359 #define APIC_LB_MAX 0xe0
358 360
359 361 #define APIC_MAX_VECTOR 255
360 362 #define APIC_RESV_VECT 0x00
361 363 #define APIC_RESV_IRQ 0xfe
362 364 #define APIC_BASE_VECT 0x20 /* This will come in as interrupt 0 */
363 365 #define APIC_AVAIL_VECTOR (APIC_MAX_VECTOR+1-APIC_BASE_VECT)
364 366 #define APIC_VECTOR_PER_IPL 0x10 /* # of vectors before PRI changes */
365 367 #define APIC_VECTOR(ipl) (apic_ipltopri[ipl] | APIC_RESV_VECT)
366 368 #define APIC_VECTOR_MASK 0x0f
367 369 #define APIC_HI_PRI_VECTS 2 /* vects reserved for hi pri reqs */
368 370 #define APIC_IPL_MASK 0xf0
369 371 #define APIC_IPL_SHIFT 4 /* >> to get ipl part of vector */
370 372 #define APIC_FIRST_FREE_IRQ 0x10
371 373 #define APIC_MAX_ISA_IRQ 15
372 374 #define APIC_IPL0 0x0f /* let IDLE_IPL be the lowest */
373 375 #define APIC_IDLE_IPL 0x00
374 376
375 377 #define APIC_MASK_ALL 0xf0 /* Mask all interrupts */
376 378
377 379 /* spurious interrupt vector */
378 380 #define APIC_SPUR_INTR 0xFF
379 381
380 382 /* special or reserve vectors */
381 383 #define APIC_CHECK_RESERVE_VECTORS(v) \
382 384 (((v) == T_FASTTRAP) || ((v) == APIC_SPUR_INTR) || \
383 385 ((v) == T_SYSCALLINT) || ((v) == T_DTRACE_RET))
384 386
385 387 /* cmos shutdown code for BIOS */
386 388 #define BIOS_SHUTDOWN 0x0a
387 389
388 390 /* define the entry types for BIOS information tables as defined in PC+MP */
389 391 #define APIC_CPU_ENTRY 0
390 392 #define APIC_BUS_ENTRY 1
391 393 #define APIC_IO_ENTRY 2
392 394 #define APIC_IO_INTR_ENTRY 3
393 395 #define APIC_LOCAL_INTR_ENTRY 4
394 396 #define APIC_MPTBL_ADDR (639 * 1024)
395 397 /*
396 398 * The MP Floating Point structure could be in 1st 1KB of EBDA or last KB
397 399 * of system base memory or in ROM between 0xF0000 and 0xFFFFF
398 400 */
399 401 #define MPFPS_RAM_WIN_LEN 1024
400 402 #define MPFPS_ROM_WIN_START (uint32_t)0xf0000
401 403 #define MPFPS_ROM_WIN_LEN 0x10000
402 404
403 405 #define EISA_LEVEL_CNTL 0x4D0
404 406
405 407 /* definitions for apic_irq_table */
406 408 #define FREE_INDEX (short)-1 /* empty slot */
407 409 #define RESERVE_INDEX (short)-2 /* ipi, softintr, clkintr */
408 410 #define ACPI_INDEX (short)-3 /* ACPI */
409 411 #define MSI_INDEX (short)-4 /* MSI */
410 412 #define MSIX_INDEX (short)-5 /* MSI-X */
411 413 #define DEFAULT_INDEX (short)0x7FFF
412 414 /* biggest positive no. to avoid conflict with actual index */
413 415
414 416 #define APIC_IS_MSI_OR_MSIX_INDEX(index) \
415 417 ((index) == MSI_INDEX || (index) == MSIX_INDEX)
416 418
417 419 /*
418 420 * definitions for MSI Address
419 421 */
420 422 #define MSI_ADDR_HDR APIC_LOCAL_ADDR
421 423 #define MSI_ADDR_DEST_SHIFT 12 /* Destination CPU's apic id */
422 424 #define MSI_ADDR_RH_FIXED 0x0 /* Redirection Hint Fixed */
423 425 #define MSI_ADDR_RH_LOPRI 0x1 /* Redirection Hint Lowest priority */
424 426 #define MSI_ADDR_RH_SHIFT 3
425 427 #define MSI_ADDR_DM_PHYSICAL 0x0 /* Physical Destination Mode */
426 428 #define MSI_ADDR_DM_LOGICAL 0x1 /* Logical Destination Mode */
427 429 #define MSI_ADDR_DM_SHIFT 2
428 430
429 431 /*
430 432 * TM is either edge or level.
431 433 */
432 434 #define TRIGGER_MODE_EDGE 0x0 /* edge sensitive */
433 435 #define TRIGGER_MODE_LEVEL 0x1 /* level sensitive */
434 436
435 437 /*
436 438 * definitions for MSI Data
437 439 */
438 440 #define MSI_DATA_DELIVERY_FIXED 0x0 /* Fixed delivery */
439 441 #define MSI_DATA_DELIVERY_LOPRI 0x1 /* Lowest priority delivery */
440 442 #define MSI_DATA_DELIVERY_SMI 0x2
441 443 #define MSI_DATA_DELIVERY_NMI 0x4
442 444 #define MSI_DATA_DELIVERY_INIT 0x5
443 445 #define MSI_DATA_DELIVERY_EXTINT 0x7
444 446 #define MSI_DATA_DELIVERY_SHIFT 8
445 447 #define MSI_DATA_TM_EDGE TRIGGER_MODE_EDGE
446 448 #define MSI_DATA_TM_LEVEL TRIGGER_MODE_LEVEL
447 449 #define MSI_DATA_TM_SHIFT 15
448 450 #define MSI_DATA_LEVEL_DEASSERT 0x0
449 451 #define MSI_DATA_LEVEL_ASSERT 0x1 /* Edge always assert */
450 452 #define MSI_DATA_LEVEL_SHIFT 14
451 453
452 454 /*
453 455 * use to define each irq setup by the apic
454 456 */
455 457 typedef struct apic_irq {
456 458 short airq_mps_intr_index; /* index into mps interrupt entries */
457 459 /* table */
458 460 uchar_t airq_intin_no;
459 461 uchar_t airq_ioapicindex;
460 462 dev_info_t *airq_dip; /* device corresponding to this interrupt */
461 463 /*
462 464 * IRQ could be shared (in H/W) in which case dip & major will be
463 465 * for the one that was last added at this level. We cannot keep a
464 466 * linked list as delspl does not tell us which device has just
465 467 * been unloaded. For most servers where we are worried about
466 468 * performance, interrupt should not be shared & should not be
467 469 * a problem. This does not cause any correctness issue - dip is
468 470 * used only as an optimisation to avoid going thru all the tables
469 471 * in translate IRQ (which is always called twice due to brokenness
470 472 * in the way IPLs are determined for devices). major is used only
471 473 * to bind interrupts corresponding to the same device on the same
472 474 * CPU. Not finding major will just cause it to be potentially bound
473 475 * to another CPU.
474 476 */
475 477 major_t airq_major; /* major number corresponding to the device */
476 478 ushort_t airq_rdt_entry; /* level, polarity & trig mode */
477 479 uint32_t airq_cpu; /* target CPU, non-reserved IRQ only */
478 480 uint32_t airq_temp_cpu; /* non-reserved IRQ only, for disable_intr */
479 481 uchar_t airq_vector; /* Vector chosen for this irq */
480 482 uchar_t airq_share; /* number of interrupts at this irq */
481 483 uchar_t airq_share_id; /* id to identify source from irqno */
482 484 uchar_t airq_ipl; /* The ipl at which this is handled */
483 485 iflag_t airq_iflag; /* interrupt flag */
484 486 uchar_t airq_origirq; /* original irq passed in */
485 487 uint_t airq_busy; /* How frequently did clock find */
486 488 /* us in this */
487 489 struct apic_irq *airq_next; /* chain of intpts sharing a vector */
488 490 void *airq_intrmap_private; /* intr remap private data */
489 491 } apic_irq_t;
490 492
491 493 #define IRQ_USER_BOUND 0x80000000 /* user requested bind if set in airq_cpu */
492 494 #define IRQ_UNBOUND (uint32_t)-1 /* set in airq_cpu and airq_temp_cpu */
493 495 #define IRQ_UNINIT (uint32_t)-2 /* in airq_temp_cpu till addspl called */
494 496
495 497 /* Macros to help deal with shared interrupts */
496 498 #define VIRTIRQ(irqno, share_id) ((irqno) | ((share_id) << 8))
497 499 #define IRQINDEX(irq) ((irq) & 0xFF) /* Mask to get irq from virtual irq */
498 500
499 501 /*
500 502 * We align apic_cpus_info at 64-byte cache line boundary. Please make sure we
501 503 * adjust APIC_PADSZ as we add/modify any member of apic_cpus_info. We also
502 504 * don't want the compiler to optimize apic_cpus_info.
503 505 */
504 506 #define APIC_PADSZ 15
505 507
506 508 #pragma pack(1)
507 509 typedef struct apic_cpus_info {
508 510 uint32_t aci_local_id;
509 511 uchar_t aci_local_ver;
510 512 uchar_t aci_status;
511 513 uchar_t aci_redistribute; /* Selected for redistribution */
512 514 uint_t aci_busy; /* Number of ticks we were in ISR */
513 515 uint_t aci_spur_cnt; /* # of spurious intpts on this cpu */
514 516 uint_t aci_ISR_in_progress; /* big enough to hold 1 << MAXIPL */
515 517 uchar_t aci_curipl; /* IPL of current ISR */
516 518 uchar_t aci_current[MAXIPL]; /* Current IRQ at each IPL */
517 519 uint32_t aci_bound; /* # of user requested binds ? */
518 520 uint32_t aci_temp_bound; /* # of non user IRQ binds */
519 521 uint32_t aci_processor_id; /* Only used in ACPI mode. */
520 522 uchar_t aci_idle; /* The CPU is idle */
521 523 /*
522 524 * Fill to make sure each struct is in separate 64-byte cache line.
523 525 */
524 526 uchar_t aci_pad[APIC_PADSZ]; /* padding for 64-byte cache line */
525 527 } apic_cpus_info_t;
526 528 #pragma pack()
527 529
528 530 #define APIC_CPU_ONLINE 0x1
529 531 #define APIC_CPU_INTR_ENABLE 0x2
530 532 #define APIC_CPU_FREE 0x4 /* APIC CPU slot is free */
531 533 #define APIC_CPU_DIRTY 0x8 /* Slot was once used */
532 534 #define APIC_CPU_SUSPEND 0x10
533 535
534 536 /*
535 537 * APIC ops to support various flavors of APIC like APIC and x2APIC.
536 538 */
537 539 typedef struct apic_regs_ops {
538 540 uint64_t (*apic_read)(uint32_t);
539 541 void (*apic_write)(uint32_t, uint64_t);
540 542 int (*apic_get_pri)(void);
541 543 void (*apic_write_task_reg)(uint64_t);
542 544 void (*apic_write_int_cmd)(uint32_t, uint32_t);
543 545 void (*apic_send_eoi)(uint32_t);
544 546 } apic_reg_ops_t;
545 547
546 548 /*
547 549 * interrupt structure for ioapic and msi
548 550 */
549 551 typedef struct ioapic_rdt {
550 552 uint32_t ir_lo;
551 553 uint32_t ir_hi;
552 554 } ioapic_rdt_t;
553 555
554 556 typedef struct msi_regs {
555 557 uint32_t mr_data;
556 558 uint64_t mr_addr;
557 559 }msi_regs_t;
558 560
559 561 /*
560 562 * APIC ops to support intel interrupt remapping
561 563 */
562 564 typedef struct apic_intrmap_ops {
563 565 int (*apic_intrmap_init)(int);
564 566 void (*apic_intrmap_enable)(int);
565 567 void (*apic_intrmap_alloc_entry)(void **, dev_info_t *, uint16_t,
566 568 int, uchar_t);
567 569 void (*apic_intrmap_map_entry)(void *, void *, uint16_t, int);
568 570 void (*apic_intrmap_free_entry)(void **);
569 571 void (*apic_intrmap_record_rdt)(void *, ioapic_rdt_t *);
570 572 void (*apic_intrmap_record_msi)(void *, msi_regs_t *);
571 573 } apic_intrmap_ops_t;
572 574
573 575 /*
574 576 * Various poweroff methods and ports & bits for them
575 577 */
576 578 #define APIC_POWEROFF_NONE 0
577 579 #define APIC_POWEROFF_VIA_RTC 1
578 580 #define APIC_POWEROFF_VIA_ASPEN_BMC 2
579 581 #define APIC_POWEROFF_VIA_SITKA_BMC 3
580 582
581 583 /* For RTC */
582 584 #define RTC_REGA 0x0a
583 585 #define PFR_REG 0x4a /* extended control register */
584 586 #define PAB_CBIT 0x08
585 587 #define WF_FLAG 0x02
586 588 #define KS_FLAG 0x01
587 589 #define EXT_BANK 0x10
588 590
589 591 /* For Aspen/Drake BMC */
590 592
591 593 #define CC_SMS_GET_STATUS 0x40
592 594 #define CC_SMS_WR_START 0x41
593 595 #define CC_SMS_WR_NEXT 0x42
594 596 #define CC_SMS_WR_END 0x43
595 597
596 598 #define MISMIC_DATA_REGISTER 0x0ca9
597 599 #define MISMIC_CNTL_REGISTER 0x0caa
598 600 #define MISMIC_FLAG_REGISTER 0x0cab
599 601
600 602 #define MISMIC_BUSY_MASK 0x01
601 603
602 604 /* For Sitka/Cabrillo BMC */
603 605
604 606 #define SMS_GET_STATUS 0x60
605 607 #define SMS_WRITE_START 0x61
606 608 #define SMS_WRITE_END 0x62
607 609
608 610 #define SMS_DATA_REGISTER 0x0ca2
609 611 #define SMS_STATUS_REGISTER 0x0ca3
610 612 #define SMS_COMMAND_REGISTER 0x0ca3
611 613
612 614 #define SMS_IBF_MASK 0x02
613 615 #define SMS_STATE_MASK 0xc0
614 616
615 617 #define SMS_IDLE_STATE 0x00
616 618 #define SMS_READ_STATE 0x40
617 619 #define SMS_WRITE_STATE 0x80
618 620 #define SMS_ERROR_STATE 0xc0
619 621
620 622 extern uint32_t ioapic_read(int ioapic_ix, uint32_t reg);
621 623 extern void ioapic_write(int ioapic_ix, uint32_t reg, uint32_t value);
622 624 extern void ioapic_write_eoi(int ioapic_ix, uint32_t value);
623 625
624 626 /* Macros for reading/writing the IOAPIC RDT entries */
625 627 #define READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, ipin) \
626 628 ioapic_read(ioapic_ix, APIC_RDT_CMD + (2 * (ipin)))
627 629
628 630 #define READ_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapic_ix, ipin) \
629 631 ioapic_read(ioapic_ix, APIC_RDT_CMD2 + (2 * (ipin)))
630 632
631 633 #define WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, ipin, value) \
632 634 ioapic_write(ioapic_ix, APIC_RDT_CMD + (2 * (ipin)), value)
633 635
634 636 #define WRITE_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapic_ix, ipin, value) \
635 637 ioapic_write(ioapic_ix, APIC_RDT_CMD2 + (2 * (ipin)), value)
636 638
637 639 /* Used by PSM_INTR_OP_GET_INTR to return device information. */
638 640 typedef struct {
639 641 uint16_t avgi_req_flags; /* request flags - to kernel */
640 642 uint8_t avgi_num_devs; /* # devs on this ino - from kernel */
641 643 uint8_t avgi_vector; /* vector */
642 644 uint32_t avgi_cpu_id; /* cpu of interrupt - from kernel */
643 645 dev_info_t **avgi_dip_list; /* kmem_alloc'ed list of dev_infos. */
644 646 /* Contains num_devs elements. */
645 647 } apic_get_intr_t;
646 648
647 649 /* Used by PSM_INTR_OP_GET_TYPE to return platform information. */
648 650 typedef struct {
649 651 char *avgi_type; /* platform type - from kernel */
650 652 uint32_t avgi_num_intr; /* max intr number - from kernel */
651 653 uint32_t avgi_num_cpu; /* max cpu number - from kernel */
652 654 } apic_get_type_t;
653 655
654 656 /* Masks for avgi_req_flags. */
655 657 #define PSMGI_REQ_CPUID 0x1 /* Request CPU ID */
656 658 #define PSMGI_REQ_NUM_DEVS 0x2 /* Request num of devices on vector */
657 659 #define PSMGI_REQ_VECTOR 0x4
658 660 #define PSMGI_REQ_GET_DEVS 0x8 /* Request device list */
659 661 #define PSMGI_REQ_ALL 0xf /* Request everything */
660 662
661 663 /* Other flags */
662 664 #define PSMGI_INTRBY_VEC 0 /* Vec passed. xlate to IRQ needed */
663 665 #define PSMGI_INTRBY_IRQ 0x8000 /* IRQ passed. no xlate needed */
664 666 #define PSMGI_INTRBY_DEFAULT 0x4000 /* PSM specific default value */
665 667 #define PSMGI_INTRBY_FLAGS 0xc000 /* Mask for this flag */
666 668
667 669 extern int apic_verbose;
668 670
669 671 /* Flag definitions for apic_verbose */
670 672 #define APIC_VERBOSE_IOAPIC_FLAG 0x00000001
671 673 #define APIC_VERBOSE_IRQ_FLAG 0x00000002
672 674 #define APIC_VERBOSE_POWEROFF_FLAG 0x00000004
673 675 #define APIC_VERBOSE_POWEROFF_PAUSE_FLAG 0x00000008
674 676 #define APIC_VERBOSE_INIT 0x00000010
675 677 #define APIC_VERBOSE_REBIND 0x00000020
676 678 #define APIC_VERBOSE_ALLOC 0x00000040
677 679 #define APIC_VERBOSE_IPI 0x00000080
678 680 #define APIC_VERBOSE_INTR 0x00000100
679 681
680 682 /* required test to wait until APIC command is sent on the bus */
681 683 #define APIC_AV_PENDING_SET() \
682 684 while (apic_reg_ops->apic_read(APIC_INT_CMD1) & AV_PENDING) \
683 685 apic_ret();
684 686
685 687 #ifdef DEBUG
686 688
687 689 #define DENT 0x0001
688 690 extern int apic_debug;
689 691 /*
690 692 * set apic_restrict_vector to the # of vectors we want to allow per range
691 693 * useful in testing shared interrupt logic by setting it to 2 or 3
692 694 */
693 695 extern int apic_restrict_vector;
694 696
695 697 #define APIC_DEBUG_MSGBUFSIZE 2048
696 698 extern int apic_debug_msgbuf[];
697 699 extern int apic_debug_msgbufindex;
698 700
699 701 /*
700 702 * Put "int" info into debug buffer. No MP consistency, but light weight.
701 703 * Good enough for most debugging.
702 704 */
703 705 #define APIC_DEBUG_BUF_PUT(x) \
704 706 apic_debug_msgbuf[apic_debug_msgbufindex++] = x; \
705 707 if (apic_debug_msgbufindex >= (APIC_DEBUG_MSGBUFSIZE - NCPU)) \
706 708 apic_debug_msgbufindex = 0;
707 709
708 710 #define APIC_VERBOSE(flag, fmt) \
709 711 if (apic_verbose & APIC_VERBOSE_##flag) \
710 712 cmn_err fmt;
711 713
712 714 #define APIC_VERBOSE_POWEROFF(fmt) \
713 715 if (apic_verbose & APIC_VERBOSE_POWEROFF_FLAG) \
714 716 prom_printf fmt;
715 717
716 718 #else /* DEBUG */
717 719
718 720 #define APIC_VERBOSE(flag, fmt)
719 721 #define APIC_VERBOSE_POWEROFF(fmt)
720 722
721 723 #endif /* DEBUG */
722 724
723 725 #define APIC_VERBOSE_IOAPIC(fmt) APIC_VERBOSE(IOAPIC_FLAG, fmt)
724 726 #define APIC_VERBOSE_IRQ(fmt) APIC_VERBOSE(IRQ_FLAG, fmt)
725 727
726 728 extern int apic_error;
727 729 /* values which apic_error can take. Not catastrophic, but may help debug */
728 730 #define APIC_ERR_BOOT_EOI 0x1
729 731 #define APIC_ERR_GET_IPIVECT_FAIL 0x2
730 732 #define APIC_ERR_INVALID_INDEX 0x4
731 733 #define APIC_ERR_MARK_VECTOR_FAIL 0x8
732 734 #define APIC_ERR_APIC_ERROR 0x40000000
733 735 #define APIC_ERR_NMI 0x80000000
734 736
735 737 /*
736 738 * ACPI definitions
737 739 */
738 740 /* _PIC method arguments */
739 741 #define ACPI_PIC_MODE 0
740 742 #define ACPI_APIC_MODE 1
741 743
742 744 /* APIC error flags we care about */
743 745 #define APIC_SEND_CS_ERROR 0x01
744 746 #define APIC_RECV_CS_ERROR 0x02
745 747 #define APIC_CS_ERRORS (APIC_SEND_CS_ERROR|APIC_RECV_CS_ERROR)
746 748
747 749 /* Maximum number of times to retry reprogramming at apic_intr_exit time */
748 750 #define APIC_REPROGRAM_MAX_TRIES 10000
749 751
750 752 /* Parameter to ioapic_init_intr(): Should ioapic ints be masked? */
751 753 #define IOAPIC_MASK 1
752 754 #define IOAPIC_NOMASK 0
753 755
754 756 #define INTR_ROUND_ROBIN_WITH_AFFINITY 0
755 757 #define INTR_ROUND_ROBIN 1
756 758 #define INTR_LOWEST_PRIORITY 2
757 759
758 760 struct ioapic_reprogram_data {
759 761 boolean_t done;
760 762 apic_irq_t *irqp;
761 763 /* The CPU to which the int will be bound */
762 764 int bindcpu;
763 765 /* # times the reprogram timeout was called */
764 766 unsigned tries;
765 767 };
766 768
767 769 /* The irq # is implicit in the array index: */
768 770 extern struct ioapic_reprogram_data apic_reprogram_info[];
769 771
770 772 extern void apic_intr_exit(int ipl, int irq);
771 773 extern void x2apic_intr_exit(int ipl, int irq);
772 774 extern int apic_probe_common();
773 775 extern void apic_init_common();
774 776 extern void ioapic_init_intr();
775 777 extern void ioapic_disable_redirection();
776 778 extern int apic_addspl_common(int irqno, int ipl, int min_ipl, int max_ipl);
777 779 extern int apic_delspl_common(int irqno, int ipl, int min_ipl, int max_ipl);
778 780 extern void apic_cleanup_busy();
779 781 extern void apic_intr_redistribute();
780 782 extern uchar_t apic_xlate_vector(uchar_t vector);
781 783 extern uchar_t apic_allocate_vector(int ipl, int irq, int pri);
782 784 extern void apic_free_vector(uchar_t vector);
783 785 extern int apic_allocate_irq(int irq);
784 786 extern uint32_t apic_bind_intr(dev_info_t *dip, int irq, uchar_t ioapicid,
785 787 uchar_t intin);
786 788 extern int apic_rebind(apic_irq_t *irq_ptr, int bind_cpu,
787 789 struct ioapic_reprogram_data *drep);
788 790 extern int apic_rebind_all(apic_irq_t *irq_ptr, int bind_cpu);
789 791 extern int apic_introp_xlate(dev_info_t *dip, struct intrspec *ispec, int type);
790 792 extern int apic_intr_ops(dev_info_t *dip, ddi_intr_handle_impl_t *hdlp,
791 793 psm_intr_op_t intr_op, int *result);
792 794 extern int apic_state(psm_state_request_t *);
793 795 extern boolean_t apic_cpu_in_range(int cpu);
794 796 extern int apic_check_msi_support();
795 797 extern apic_irq_t *apic_find_irq(dev_info_t *dip, struct intrspec *ispec,
796 798 int type);
797 799 extern int apic_navail_vector(dev_info_t *dip, int pri);
798 800 extern int apic_alloc_msi_vectors(dev_info_t *dip, int inum, int count,
799 801 int pri, int behavior);
800 802 extern int apic_alloc_msix_vectors(dev_info_t *dip, int inum, int count,
801 803 int pri, int behavior);
802 804 extern void apic_free_vectors(dev_info_t *dip, int inum, int count, int pri,
803 805 int type);
804 806 extern int apic_get_vector_intr_info(int vecirq,
805 807 apic_get_intr_t *intr_params_p);
806 808 extern uchar_t apic_find_multi_vectors(int pri, int count);
807 809 extern int apic_setup_io_intr(void *p, int irq, boolean_t deferred);
808 810 extern uint32_t *mapin_apic(uint32_t addr, size_t len, int flags);
809 811 extern uint32_t *mapin_ioapic(uint32_t addr, size_t len, int flags);
810 812 extern void mapout_apic(caddr_t addr, size_t len);
811 813 extern void mapout_ioapic(caddr_t addr, size_t len);
812 814 extern uchar_t apic_modify_vector(uchar_t vector, int irq);
813 815 extern void apic_pci_msi_unconfigure(dev_info_t *rdip, int type, int inum);
814 816 extern void apic_pci_msi_disable_mode(dev_info_t *rdip, int type);
815 817 extern void apic_pci_msi_enable_mode(dev_info_t *rdip, int type, int inum);
816 818 extern void apic_pci_msi_enable_vector(apic_irq_t *, int type, int inum,
817 819 int vector, int count, int target_apic_id);
818 820 extern char *apic_get_apic_type();
819 821 extern uint16_t apic_get_apic_version();
820 822 extern void x2apic_send_ipi();
821 823 extern void apic_ret();
822 824 extern int apic_detect_x2apic();
823 825 extern void apic_enable_x2apic();
824 826 extern int apic_local_mode();
825 827 extern void apic_change_eoi();
826 828 extern void apic_send_EOI(uint32_t);
827 829 extern void apic_send_directed_EOI(uint32_t);
828 830 extern uint_t apic_calibrate(volatile uint32_t *, uint16_t *);
829 831
830 832 extern volatile uint32_t *apicadr; /* virtual addr of local APIC */
831 833 extern int apic_forceload;
832 834 extern apic_cpus_info_t *apic_cpus;
833 835 #ifdef _MACHDEP
834 836 extern cpuset_t apic_cpumask;
835 837 #endif
836 838 extern uint_t apic_picinit_called;
837 839 extern uchar_t apic_ipltopri[MAXIPL+1];
838 840 extern uchar_t apic_vector_to_irq[APIC_MAX_VECTOR+1];
839 841 extern int apic_max_device_irq;
840 842 extern int apic_min_device_irq;
841 843 extern apic_irq_t *apic_irq_table[APIC_MAX_VECTOR+1];
842 844 extern volatile uint32_t *apicioadr[MAX_IO_APIC];
843 845 extern uchar_t apic_io_id[MAX_IO_APIC];
844 846 extern lock_t apic_ioapic_lock;
845 847 extern uint32_t apic_physaddr[MAX_IO_APIC];
846 848 extern kmutex_t airq_mutex;
847 849 extern int apic_first_avail_irq;
848 850 extern uchar_t apic_vectortoipl[APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL];
849 851 extern int apic_imcrp;
850 852 extern int apic_revector_pending;
851 853 extern char apic_level_intr[APIC_MAX_VECTOR+1];
852 854 extern uchar_t apic_resv_vector[MAXIPL+1];
853 855 extern int apic_sample_factor_redistribution;
854 856 extern int apic_int_busy_mark;
855 857 extern int apic_int_free_mark;
856 858 extern int apic_diff_for_redistribution;
857 859 extern int apic_poweroff_method;
858 860 extern int apic_enable_acpi;
859 861 extern int apic_nproc;
860 862 extern int apic_max_nproc;
861 863 extern int apic_next_bind_cpu;
862 864 extern int apic_redistribute_sample_interval;
863 865 extern int apic_multi_msi_enable;
864 866 extern int apic_sci_vect;
865 867 extern int apic_hpet_vect;
866 868 extern uchar_t apic_ipls[];
867 869 extern apic_reg_ops_t *apic_reg_ops;
868 870 extern int apic_mode;
869 871 extern void x2apic_update_psm();
870 872 extern void apic_change_ops();
871 873 extern void apic_common_send_ipi(int, int);
872 874 extern void apic_set_directed_EOI_handler();
873 875 extern int apic_directed_EOI_supported();
874 876
875 877 extern apic_intrmap_ops_t *apic_vt_ops;
876 878
877 879 #ifdef __cplusplus
878 880 }
879 881 #endif
880 882
881 883 #endif /* _SYS_APIC_APIC_H */
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